E.J. Nowak

Bio: E.J. Nowak is an academic researcher from IBM. The author has contributed to research in topics: CMOS & MOSFET. The author has an hindex of 13, co-authored 17 publications receiving 1257 citations.

Turning silicon on its edge [double gate CMOS/FinFET technology]

Abstract: Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

Extension and source/drain design for high-performance FinFET devices

Abstract: Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.

Low-power CMOS at Vdd = 4kT/q

Abstract: Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic.

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

Abstract: A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date Short channel effect control down to 35 nm is demonstrated Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance

A functional FinFET-DGCMOS SRAM cell

Abstract: An operational six-transistor SRAM cell is experimentally demonstrated using Double Gate CMOS FinFET technology. A cell size of 4.8 /spl mu/m/sup 2/ was achieved in 180 nm node technology, with stable operation at 1.5 V using a single level of copper interconnect. To our knowledge this represents the first experimental demonstration of a fully integrated FinFET SRAM Cell.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

Abstract: A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm

High-performance CMOS variability in the 65-nm regime and beyond

Abstract: Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Abstract: This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.