Author
E. J. Rymaszewski
Bio: E. J. Rymaszewski is an academic researcher from Rensselaer Polytechnic Institute. The author has contributed to research in topics: Thin film & Dielectric. The author has an hindex of 11, co-authored 21 publications receiving 1600 citations.
Topics: Thin film, Dielectric, Capacitor, High-κ dielectric, Amorphous solid
Papers
More filters
TL;DR: In this paper, a relatively simple direct current sputtering deposition scheme has been employed to deposit 1000 A tantalum oxide thin films at low temperature, without further annealing, and these properties are achieved over a wide range of O2/Ar ratios when the total flow rate is kept constant.
Abstract: A relatively simple direct current sputtering deposition scheme has been employed to deposit 1000 A tantalum oxide thin films at low temperature. At ≂190 °C substrate temperature, without further annealing, tantalum oxide films with a dielectric constant of 21–22 and a leakage current density as low as 10 nA/cm2 at 0.5 MV/cm electrical field strength (∼5 V of applied voltage) are obtained. These properties are achieved over a wide range of O2/Ar ratios when the total flow rate is kept constant. XPS measurements reveal that these films are nonstoichiometric with a composition of TaOx where x≂1.5. These low temperature, high dielectric constant thin films have potential applications as decoupling capacitors in very high speed electronic circuits and packaging.
43 citations
Book•
30 Nov 2003
TL;DR: In this article, the authors present a characterization of thin-film capacitors and show that they can be used in 3D ICs for large-area power distribution, including 2D and 3D packaging.
Abstract: Preface. Acknowledgements. 1: Introduction. 1.1. Capacitor Fundamentals. 1.2. Application Domains. 1.3. Physical Structures/Embodiments. 1.4. Capacitor Integration Drivers. 1.5. Thin-Film Capacitor Technology. 1.6. Summary. 1.7. References. 2: Design Fundamentals. 2.1. Breakdown Voltage and Capacitance Density Design Limits. 2.2. Tolerance in Capacitance Density. 2.3. DC Leakage. 2.4. Capacitor Losses. 2.5. Series Inductance and Resistance. 2.6. References. 3: Performance Detractors. 3.1. Interfacial Micro-roughness. 3.2. Deviation from Optimal Stoichiometry. 3.3. Film Microstructure. 3.4. References. 4: Electrical Characterization. 4.1. Thin Film Decoupling Capacitors. 4.2. Characterization Methodologies. 4.3. Test Vehicle: Design and Fabrication. 4.4. Dielectric Constant and Loss. 4.5. Total Series Inductance. 4.6. Leakage Current Density. 4.7. Capacitance Density and Breakdown Field. 4.8. Summary and Conclusion. 4.9. References. 5: Integration Issues And Challenges. 5.1. Metal Diffusion into Dielectrics. 5.2. Interlayer Stresses and Adhesion. 5.3. Low Thermal Budget. 5.4. References. 6: Applications. 6.1. 2D Interconnections in ICs. 6.2. Integration into 2D Packaging. 6.3. Flex Circuits. 6.4. Large Area Power Distribution. 6.5. Integration into 3D Structures. 6.6. Electromagnetic Considerations. 6.7. Power Electronics. 6.8. References. Index.
39 citations
TL;DR: In this article, the peak decomposition technique was employed to identify the composition and chemical states at the interface region of thin Al/Ta2O5 and Ta2O3/Al films using the x-ray photoelectron spectroscopy technique.
Abstract: Buried interfaces of thin Al/Ta2O5 and Ta2O5/Al films were studied using the x-ray photoelectron spectroscopy technique. The peak decomposition technique was employed to identify the composition and chemical states at the interface region. It was observed that there is an “intermixing layer” at the Al/Ta2O5 interface, where Ta2O5 has been reduced to lower binding energy states due to the reaction of Al with Ta2O5 during deposition. On the other hand, the Ta2O5/Al interface is relatively stable, consisting of Ta2O5 and Al2O3 interfacial layers. Based on a uniform multilayer structure model, the thickness of the interfacial layers was estimated by using the relative photoelectron intensities.
37 citations
TL;DR: In this paper, a Tantalum oxide thin film capacitors were fabricated on metallized polyimide sheet substrates and tested and it was found that the substrate's surface topography has a strong influence on the electrical properties and yields of the capacitors.
Abstract: Tantalum oxide thin film capacitors were fabricated on metallized polyimide sheet substrates and tested. It was found that the substrates' surface topography has a strong influence on the electrical properties and yields of the thin film capacitors. The leakage current density and breakdown field strength of the capacitors are qualitatively correlated to the amount and degree of surface irregularities on the substrates, which were analyzed using scanning electron microscopy (SEM), atomic force microscopy (AFM), and profilometry. It was demonstrated that Benzocyclobutene (BCB) can be used to planarize the surface irregularities and to improve the capacitor yield and performance. The importance of choosing the right substrate materials for thin film capacitor fabrication is also discussed.
27 citations
Cited by
More filters
TL;DR: In this paper, a number of cubic crystals, two-dimensional layered materials, nanostructure networks and composites, molecular layers and surface functionalization, and aligned polymer structures are examined for potential applications as heat spreading layers and substrates, thermal interface materials, and underfill materials in future-generation electronics.
1,269 citations
TL;DR: An overview of antenna design for passive radio frequency identification (RFID) tags is presented, which outlines a generic design process including range measurement techniques and focuses on one practical application: RFID tag for box tracking in warehouses.
Abstract: In this paper, an overview of antenna design for passive radio frequency identification (RFID) tags is presented. We discuss various requirements of such designs, outline a generic design process including range measurement techniques and concentrate on one practical application: RFID tag for box tracking in warehouses. A loaded meander antenna design for this application is described and its various practical aspects such as sensitivity to fabrication process and box content are analyzed. Modeling and simulation results are also presented which are in good agreement with measurement data.
1,268 citations
TL;DR: In this article, the authors present the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies.
Abstract: This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.
627 citations
TL;DR: A review of the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications can be found in this paper, where the main advantages of this technique include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers.
Abstract: Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronic and microelectromechanical systems, such as three-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive bears the forces involved to hold the surfaces together. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers. Compared to alternative wafer bonding techniques, adhesive wafer bonding is simple, robust, and low cost. This article reviews the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications.
494 citations
IBM1
TL;DR: 3D technology from IBM is highlighted, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and examples of 3D emerging industry product applications that could create marketable systems are provided.
Abstract: Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.
461 citations