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Author

E. Konguvel

Other affiliations: Anna University
Bio: E. Konguvel is an academic researcher from Madras Institute of Technology. The author has contributed to research in topics: Fast Fourier transform & Very-large-scale integration. The author has an hindex of 5, co-authored 11 publications receiving 58 citations. Previous affiliations of E. Konguvel include Anna University.

Papers
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Journal ArticleDOI
TL;DR: A comparative study of efficient algorithms and architectures for FFT chip design is presented and it is recommended that mixed-radix/higher-radIX algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIM o and multi-user MIMo-based applications.
Abstract: The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.

18 citations

Proceedings ArticleDOI
01 Mar 2017
TL;DR: The design of low power Radix-8 DIT FFT is presented, which aims at reducing the number of multipliers that are used to compute the FFT by swapping the input terms and reordering them to reduce the power consumption.
Abstract: In recent years the Fast Fourier Transform is widely used in a number of applications as it is considered to be an efficient algorithm to compute the Discrete Fourier Transform. The process of computing the FFT for large sequence real time data becomes complex and tedious. Hence it is necessary to design a system that can perform the FFT computation of large sequence data with reduced power consumption. This paper presents the design of low power Radix-8 DIT FFT. The proposed design aims at reducing the number of multipliers that are used to compute the FFT. This is achieved by swapping the input terms and reordering them. This leads to a reduction in the number of multipliers used to perform the computation and thereby causing a reduction in the power consumption. This method is highly advantageous when the input signals are lengthy since the number of multipliers used is large in number consuming very high power. In order to optimize the FFT architecture the number of multipliers is reduced thereby causing a significant reduction in power. The prototype for Radix-2 (8 point) and Radix-4 (16 point) optimized FFT is designed, implemented and simulated using Altera ModelSim DE2 EP2C35F672C6 FPGA device. The proposed Radix-2 (8 point) and Radix-4 (16 point) optimized FFT operates at a speed of 10.41 Gbps and 21.23 Gbps respectively.

10 citations

Journal ArticleDOI
TL;DR: An unique method that replaces the BEC using common Boolean logic is introduced that achieves advantages in terms of speed, area consumption and power.
Abstract: Select Adder (CSLA) is one of the speedest adder utilized as a part of numerous computational frameworks to perform quick number-crunching operations. The Carry select adder utilizes an effective plan by imparting the Common Boolean logic (CLB) term. The modified CSLA architecture building design has created utilizing Binary to Excess-1 converter (BEC). This paper introduces an unique method that replaces the BEC using common Boolean logic. Experimental analysis illustrates that the proposed architecture achieves advantages in terms of speed, area consumption and power.

8 citations


Cited by
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Proceedings ArticleDOI
17 Aug 2014
TL;DR: This paper introduces the first multi-antenna cancellation design that operates on back scatter devices while retaining a small form factor and power footprint, and introduces a novel coding mechanism that enables long range communication as well as concurrent transmissions and can be decoded on backscatter devices.
Abstract: Communication primitives such as coding and multiple antenna processing have provided significant benefits for traditional wireless systems. Existing designs, however, consume significant power and computational resources, and hence cannot be run on low complexity, power constrained backscatter devices. This paper makes two main contributions: (1) we introduce the first multi-antenna cancellation design that operates on backscatter devices while retaining a small form factor and power footprint, (2) we introduce a novel coding mechanism that enables long range communication as well as concurrent transmissions and can be decoded on backscatter devices. We build hardware prototypes of the above designs that can be powered solely using harvested energy from TV and solar sources. The results show that our designs provide benefits for both RFID and ambient backscatter systems: they enable RFID tags to communicate directly with each other at distances of tens of meters and through multiple walls. They also increase the communication rate and range achieved by ambient backscatter systems by 100X and 40X respectively. We believe that this paper represents a substantial leap in the capabilities of backscatter communication.

358 citations

DOI
30 Dec 1899

263 citations

Journal ArticleDOI
TL;DR: It is shown that the effect of nonlinearity is shown to be negligible on MIMO-CE-OFDM signal, which is a promising technique for high-performance 5G broadband wireless communications.
Abstract: Orthogonal frequency division multiplexing (OFDM) is a multicarrier transmission system that can achieve high data rate over wireless channels At the same time, multiple input multiple output OFDM

20 citations

Journal ArticleDOI
TL;DR: A comparative study of efficient algorithms and architectures for FFT chip design is presented and it is recommended that mixed-radix/higher-radIX algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIM o and multi-user MIMo-based applications.
Abstract: The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.

18 citations

Patent
12 Oct 2004
TL;DR: The RAM unit main embodiment sort CAM function is used by the method to provide significantly more table entries, or provide significantly less area size of a given table.
Abstract: The present invention discloses a method by using the RAM unit main embodiment sort CAM function. Compared with a conventional three yuan the CAM, the method in a given area to provide significantly more table entries, or provide significantly less area size of a given table. The CAM as compared with conventional, the method is more power efficient, less expensive and provides a wider range of features.

17 citations