An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Tileable field-programmable gate array architecture

We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

Built-in self-test of FPGA interconnect

In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications

SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.

Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

BIST-based test and diagnosis of FPGA logic blocks : Reconfigurable and Adaptive VLSI Systems

Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance. In this paper we present the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution. Our approach is based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs. An adaptive diagnostic strategy provides identification of faulty PLBs with a 7% increase in testing time over the complete detection test, and can also be used for manufacturing yield enhancement. We present results showing identification of faulty PLBs in defective ORCA chips.

BIST-based diagnostics of FPGA logic blocks

We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.

Using ILA testing for BIST in FPGAs

A method of testing field programmable gate arrays (FPGAs) includes establishing a first group of programmable logic blocks as test pattern generators or output response analyzers and a second group of programmable logic blocks as blocks under test. This is followed by generating test patterns and comparing outputs of two blocks under test with one output response analyzer. Next is the combining of results of a plurality of output response analyzers utilizing an iterative comparator in order to produce a pass/fail indication. The method also includes the step of reconfiguring each block under test so that each block under test is tested in all possible modes of operation. Further, there follows the step of reversing programming of the groups of programmable logic blocks so that each programmable logic block is configured at least once as a block under test.

/pdf/method-of-testing-and-diagnosing-field-programmable-gate-2ttfhfgnbu.pdf

Method of testing and diagnosing field programmable gate arrays

In our previous work, we have described a built-in self-test (BIST) approach for RAM-based field programmable gate arrays (FPGAs), which exploits the reprogrammability of the FPGA to create BIST logic only during off-line testing. The cost is additional external memory required to store the BIST reconfiguration data, leaving all FPGA logic resources available for system functions. In this paper, the memory requirements as well as the testing time are minimized by selecting a few BIST configurations which provide high fault coverage for inspection tests at board and system manufacturing as well as for efficient system diagnostics and field testing.

Selecting built-in self-test configurations for field programmable gate arrays

Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-toler- ance. In this paper we present the: first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal cliagnos- tic resolution. Our approach is basecl on a new Built-In Self- Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty l?LBs. An adaptive diag- nostic strategy provides identification of faulty PLB!j with a 7% increase in testing time over the complete detect.ion test, and can also be used for manufacturing yield einhanlcement. We present results showing identification of faulty I'LBs in defective ORCA chips.' 1.Introducti.on An FPGA consists of an array of programmable logic blocks (PLBs) interconnected by a programm,able routing network, and programmable U0 cells. The set of all program- ming bits establishes a cnnjiguration which determines the function of the device. In this paper, we considler in-circuit reprogrammable FPGAs, such as SRAM-based FPGAs, which may be reconfigured an arbitrarily large: number of times. FPGA manufacturing tests are complicated by the need to cover all possible modes of operation of the PLBs and also to detect all the faults affecting the programmable inter- connect network. Currently, thesje tests are generated manually by configuring several application circuits and exercising them with test patterns developed specifically for each application circuit. The FPGA manufacturing tiests are not reusable for board and system-level testing, which require separate development efforts that rely on system diagnostic routines to test the FPGAs in their system mode of operation. The development of these diagnostic routines can be time- consuming and costly, and locating a faulty FPGA may be difficult. Previous work in FPGA te~ting(~~(~~('* ~(''~

E. Lee

Papers

BIST-based diagnostics of FPGA logic blocks

Using ILA testing for BIST in FPGAs

Method of testing and diagnosing field programmable gate arrays

Selecting built-in self-test configurations for field programmable gate arrays

BIST-Based Diaignostics of FPGA Logic Bllocks