Preface. 1. Introduction. 2. Optical Fiber. 3. Photodetectors. 4. Receiver Fundamentals. 5. Transimpledance Amplifiers. 6. Main Amplifiers. 7. Optical Transmitters. 8. Laser and Modulator Drivers. Appendix A: Eye Diagrams. Appendix B: Differential Circuits. Appendix C: S Parameters. Appendix D: Transistors and Technologies. Appendix E: Answers to the Problems. Appendix F: Notation. Appendix G: Symbols. Appendix H: Acronyms. References. Index.

Broadband Circuits for Optical Fiber Communication

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.

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10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

An analysis is given of the factors which influence the performance of a Fourier transform n.m.r. spectrometer including field homogeneity, probe design, transient circuit behaviour, Johnson noise, non linear analysis, phase sensitive detection in quadrature, and signal processing. The building of a spectrometer based upon the analysis of these factors is described, as is the use of a cyclically ordered phase sequence (CYCLOPS) which renders the use of quadrature Fourier transformation easy. Theoretical deductions are experimentally verified, and the performance of the instrument is demonstrated with spectra obtained from caesium and phosphorus resonances.

Critical factors in the design of sensitive high resolution nuclear magnetic resonance spectrometers

In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.

Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s

An optical receiver front-end for SONET OC-48 (2.5 Gb/s) is shown. The limiting amplifier (LA) receives a small-non-return to zero (NRZ) voltage signal (e.g., 8 mV/sub pp/) from the transimpedance amplifier (TIA) and amplifies it to a level (e.g. 250 mV/sub pp/) sufficient for the reliable operation of the clock and data recovery circuit. The noise contribution of the LA must be small compared to that of the TIA so that the overall bit error rate and sensitivity are not affected adversely. Currently, commercial 2.5 Gb/s SONET systems are composed of several discrete chips implemented in GaAs and more recently silicon bipolar technology. The future trend, however, is to integrate most of the front-end together with the digital framer on a single CMOS chip. Furthermore, the integration of multiple 2.5 Gb/s channels on a single CMOS chip is desirable for wavelength division multiplexing (WDM) application. CMOS amplifiers for optical receivers and related applications with bandwidths up to 2.1 GHz are recently reported. This CMOS limiting amplifier with improved bandwidth (3 GHz) and noise figure (16 dB) is suitable for 2.5 Gb/s SONET receivers. Power dissipation is 53 mW and the chip is fabricated in a standard 2.5 V, 0.25 /spl mu/m CMOS technology. This result is achieved with: (i) Inverse scaling to increase gain-bandwidth and reduce power dissipation while keeping noise and offset voltage low and (ii) active inductors to increase gain-bandwidth and improve gain stability. The active area of the amplifier is 0.03 mm/sup 2/, less than 10% that of a comparable design with spiral inductors.

A 3 GHz, 32 dB CMOS limiting amplifier for SONET OC-48 receivers

A design technique is developed which apparently overcomes all the limitations of common-emitter transistor video amplifiers. This technique is based on the use of the impedance mismatch which occurs between stages having alternate series and shunt feedback. It is shown that the realizable gain-bandwidth product is in excess of 0.9ωT, the gain and bandwidth are insensitive to transistor parameter variations, and large output voltages may be obtained. The equations for both gain and bandwidth are developed in a form which is particularly suited to practical design work, and are accurate despite their comparative simplicity.In addition to the main treatment, the design of terminal stages and of multi-stage feedback loops is considered in detail, and some aspects of the theory of noise in feedback amplifiers are discussed.Two complete design examples are described. These are a 20dB 25Mc/s amplifier for 75Ω lines using two OC170 transistors, and a vidicon head-amplifier which achieves 3 × 10−9 A noise at the input in a 5 Mc/s bandwidth.

E.M. Cherry

Papers

The design of wide-band transistor feedback amplifiers