scispace - formally typeset
Search or ask a question
Author

E. Malavasi

Bio: E. Malavasi is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Physical design & Integrated circuit layout. The author has an hindex of 13, co-authored 26 publications receiving 1014 citations. Previous affiliations of E. Malavasi include University of Padua & University of California, Berkeley.

Papers
More filters
Book
30 Nov 1996
TL;DR: A top-down, constraint-driven design methodology for analog integrated circuits and some of the tools that support this methodology are described, including behavioral simulation tools, tools for physical assembly, and module generators.
Abstract: This paper describes a top-down, constraint-driven design methodology for analog integrated circuits. Some of the tools that support this methodology are described. These include behavioral simulation tools, tools for physical assembly, and module generators. Finally, examples of behavioral simulation with optimization and physical assembly are provided to better illustrate the methodology and its integration with the tool set.

186 citations

Journal ArticleDOI
TL;DR: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented, guaranteeing that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment.
Abstract: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

162 citations

Journal ArticleDOI
TL;DR: This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.
Abstract: The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

152 citations

Patent
03 Apr 1996
TL;DR: In this paper, a structural description of an integrated circuit is converted into a constraint graph, and the constraint graph is then expanded by replacing edges having piecewise linear cost function with subgraphs constructed from the piecewiselinear cost function.
Abstract: A system, method, and software product in a computer aided design apparatus for system design, to simultaneously optimize multiple performance criteria models of the system, where the performance criteria models are characterized by convex cost functions based on linear dimensional characteristics of system being designed. One embodiment is provided in a computer aid design environment for integrated circuit design, and used to simultaneously optimize fabrication yield along with other performance criteria. Optimization is provided by converting a structural description of an integrated circuit into a constraint graph, compacting, and modifying the constraint graph to include convex cost functions for selected performance criteria to optimized, such as yield cost functions. The cost functions are then transformed to piecewise linear cost functions. The constraint graph is then expanded by replacing edges having piecewise linear cost function with subgraphs constructed from the piecewise linear cost function. The expanded constraint graph is then minimized using a network flow algorithm. Once minimized, the constraint graph describes the positions of circuit elements that maximize yield (and other selected performance criteria) given the cost functions.

107 citations

Proceedings ArticleDOI
03 May 1992
TL;DR: A new constraint-driven methodology for the placeinent of analog IC's is described, where electrical performance specifications are automatically translated into constraints on the layout parasitics and these constraints and the seiisiitivity iiiforinatioii of the circuit are used to control a Simulated Annealingbased placement algorithm.
Abstract: A new constraint-driven methodology for the placeinent of analog IC's is described. Electrical performance specifications are automatically translated into constraints on the layout parasitics. These constraints and the seiisiitivity iiiforinatioii of the circuit are then used to control a Simulated Annealingbased placement algorithm. At each step of the annealing a fast check on performance degradations is performed to guarantee that the tool has the necessary robur,tness.

57 citations


Cited by
More filters
Book
31 Jan 1993
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

927 citations

Journal ArticleDOI
01 Dec 2000
TL;DR: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs) and outlines progress on the various design problems involved.
Abstract: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

579 citations

Journal Article
TL;DR: In this article, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. And the authors showed that in such cases the substrate noise is highly dependent on layout geometry.
Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

567 citations

Journal ArticleDOI
TL;DR: A new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps) is described, showing in detail how the method can be used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
Abstract: We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

540 citations