E
E. Malavasi
Researcher at Cadence Design Systems
Publications - 26
Citations - 1033
E. Malavasi is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Physical design & Integrated circuit layout. The author has an hindex of 13, co-authored 26 publications receiving 1014 citations. Previous affiliations of E. Malavasi include University of Padua & University of California, Berkeley.
Papers
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Journal ArticleDOI
Area routing for analog layout
TL;DR: An area router specifically tailored for the layout of analog circuits is presented, based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency.
Proceedings ArticleDOI
Generalized constraint generation for analog circuit design
TL;DR: A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits.
Proceedings ArticleDOI
A routing methodology for analog integrated circuits
TL;DR: A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described, and sensitivities of performance to parasitics are computed, and a set of bounding constraints for Parasitics is determined.
Proceedings ArticleDOI
Enhanced network flow algorithm for yield optimization
Cyrus Bamji,E. Malavasi +1 more
TL;DR: A novel constraint-graph algorithm is presented that improves the yield of a layout by carefully spacing objects to reduce the probability of faults due to spot defects and can in theory provide the best possible yield achievable without modifying the layout topology.
Proceedings ArticleDOI
Top-down, constraint-driven design methodology based generation of n-bit interpolative current source D/A converters
Henry Chang,E. Liu,R. Neff,Eric Felt,E. Malavasi,Edoardo Charbon,Alberto Sangiovanni-Vincentelli,Paul R. Gray +7 more
TL;DR: In this article, a top-down, constraint-driven design methodology is proposed to accelerate the design cycle for analog circuits and mixed-signal systems, and a design which demonstrates the two principal advantages that this methodology provides-a high probability for first silicon which meets all specifications and fast design times.