E. Papanasam

Bio: E. Papanasam is an academic researcher from Indian Institutes of Information Technology. The author has contributed to research in topics: Capacitor & Gate dielectric. The author has an hindex of 1, co-authored 4 publications receiving 4 citations. Previous affiliations of E. Papanasam include VIT University.

Effect of post deposition annealing and post metallization annealing on electrical and structural characteristics of Pd/Al2O3/6H-SiC MIS capacitors

Abstract: Purpose Al2O3 used as gate dielectric enables exploitation of higher electric field capacity of SiC, improving capacitive coupling and memory retention in flash memories. Passivation of traps at interface and in bulk which causes serious threat is necessary for better performance. The purpose of this paper is to investigate the effect of post-deposition rapid thermal annealing (PDA) and post-metallization annealing (PMA) on the structural and electrical characteristics of Pd/Al2O3/6H-SiC capacitors. Design/methodology/approach Al2O3 film is deposited by ALD; PDA is performed by rapid thermal annealing (RTA) in N2 at 900°C for 1 min and PMA in forming gas for 10 and 40 min. X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements data are studied in addition to capacitance-voltage (C-V) and current-voltage (I-V) characteristics for the fabricated Pd/Al2O3/SiC capacitors. Conduction mechanism contributing to the gate leakage current is extracted for the entire range of gate electric field. Findings RTA forms aluminum silicide at the interface causing an increase in the density of the interface states and gate leakage current for devices with an annealed film, when compared with an as-deposited film. One order improvement in leakage current has been observed for the devices with RTA, after subjecting to PMA for 40 min, compared with those devices for which PMA was carried out for 10 min. Whereas, no improvement in leakage current has been observed for the devices on as-deposited film, even after subjecting to PMA for 40 min. Conduction mechanisms contributing to gate leakage current are extracted for the investigated Al2O3/SiC capacitors and are found to be trapfilled limit process at low-field regions; trapassisted tunneling in the mid-field regions and Fowler–Nordheim (FN) tunneling are dominating in high-field regions. Originality/value The effect of PDA and PMA on the structural and electrical characteristics of Pd/Al2O3/SiC capacitors suitable for flash memory applications is investigated in this paper.

Effect of post metallization annealing on the electrical characteristics of Pd/HfO 2 /6H-SiC MIS capacitors and extraction of conduction mechanisms

Abstract: Effect of post metallization annealing on the electrical characteristics of Pd/HfO 2 /6H-SiC MIS capacitors are reported in this work. MIS capacitors when subjected to post metallization annealing in forming gas for longer duration (40 min) exhibited improved electrical characteristics. Density of interface states is found to be reduced by one order. Gate leakage current density is also reduced for the devices when compared with those MIS capacitors for which annealing was carried out for only 10 minutes. Minimum value of interface state density is extracted to be 6.5 ×1010 /cm2 eV and gate leakage current density of 0.47 A/cm2 is obtained at an electric field of 5 MV/cm in devices which have undergone annealing for extended duration. Conduction mechanisms contributing to leakage current in the entire range of gate electric field are also extracted and presented in this paper. Major mechanism of conduction at low electric field is determined to be Trap assisted tunneling, while Fowler-Nordheim tunneling is dominating at high electric field.

Extraction and Analysis of Gate Leakage Current Mechanism in Silicon Carbide (SiC) MIS Capacitors

Abstract: Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leak...

High-Q and FOM Dual-Band Polarization Dependent Ultra-Narrowband Terahertz Metamaterial Sensor

Abstract: Polarization-dependent dual-band THz metamaterial using a modified Trishul structure is proposed in this paper. The absorber has three layers namely, a conducting ground plane, a dielectric substrate, and a structure top metallic patch. The top and bottom metallic is made up of gold material and the dielectric substrate is polyimide. The characteristics are obtained using the finite element method. The structure has obtained two resonant peaks at 0.78 THz(f1) and 1.65 THz(f2) for the X-polarized wave and at 0.81 THz(f3) and 1.53 THz(f4) for the Y-polarized wave respectively. The simulation result reveals that the absorber has obtained ultra-narrow band absorption with a full width half maximum(FWHM) of 4.8 GHz, 10 GHz, 5 GHz, and 10 GHz for f1, f2, f3, and f4 respectively. In addition, the underlying physical mechanism of the multi-band characteristics is analyzed using electric field and surface current distributions. The proposed absorber design has importance in the emerging THz system for polarization imaging and sensing applications. Also, flexible metamaterials could be useful for soft robotics applications also.

Realization of silicon carbide MIS capacitors with high-K and high-K stack dielectric

Abstract: Silicon carbide MIS capacitors with high dielectric constant material and its stack has been designed and characterized using TCAD Sentaurus tools. Interface dipole theory on metal-dielectric interface has been used to determine the work function of gate metal on different dielectric materials. It has been found that in single dielectric with high-K material Si 3 N 4 exhibit better electrical characteristics with fixed oxide charges and interface state density of − 3.06 × 1012 / cm2 and 2.9 × 1012 /cm2 eV respectively. In high-K stack dielectric, extracted fixed oxide charges is found to be lowest in Si 3 N 4 -SiO2 stack while HfO 2 -SiO 2 stack exhibit lowest interface state density of 3.0 × 1012 /cm2 eV. Gate current density of stack dielectric at high electric field is compared with SiO 2 and is found to be lowest in ZrO 2 -SiO 2 stack dielectric.

JSS FOCUS ISSUE ON WIDE BANDGAP POWER SEMICONDUCTORS Improvement of Electrical Performance of HfO2/SiO2/4H-SiC Structure with Thin SiO2

Abstract: The impact of a thin interfacial SiO2 layer between HfO2 and SiC for the improvement of dielectric’s electrical property was investigated. Regarding the material choice of dielectric on SiC, various combinations of HfO2 and SiO2 were examined on devices by capacitance and current measurements. It was found that the thickness of SiO2 interfacial layer is critical. As SiO2 grows thicker, excess carbon is believed to be generated in SiC close to SiC/SiO2 interface as observed by X-ray photoelectron spectroscopy. The defects induced during the growth of the SiO2 layer are believed to affect the inversion region in the substrate. Excess carbon does not behave as mobile ion when examined by bias-temperature stress, and it can induce considerable electron trapping under constant bias stress. On the other hand, large capacitance voltage (C-V) frequency dispersion appears when HfO2 is directly deposited on SiC. With 7.4 nm thin SiO2 layer between HfO2 and SiC, the C-V distortion and dispersion can be significantly eliminated. The leakage current with thin SiO2 layer was significantly reduced as compared with only HfO2 on SiC. Thin SiO2 (7.4) layer is beneficial to 4H-SiC MOS capacitors with respect to their dielectric and passivation properties.

Extraction and Analysis of Gate Leakage Current Mechanism in Silicon Carbide (SiC) MIS Capacitors

Abstract: Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leak...

Properties of Cu/Zn+15%SAC0307+15%Cu/Al joints by different ultrasonic-assisted degrees

Abstract: Purpose This paper aims to investigate the effects of different ultrasonic-assisted loading degrees on the microstructure, mechanical properties and the fracture morphology of Cu/Zn+15%SAC0307+15%Cu/Al solder joints. Design/methodology/approach A new method in which 45 μm Zn particles were mixed with 15% 500 nm Cu particles and 15% 500 nm SAC0307 particles as solders (SACZ) and five different ultrasonic loading degrees were applied for realizing the soldering between Cu and Al at 240 °C and 8 MPa. Then, SEM was used to observe and analyze the soldering seam, interface microstructure and fracture morphology; the structural composition was determined by EDS; the phase of the soldering seam was characterized by XRD; and a PTR-1102 bonding tester was adopted to test the average shear strength. Findings The results manifest that Al–Zn solid solution is formed on the Al side of the Cu/SACZ/Al joints, while the interface IMC (Cu5Zn8) is formed on the Cu side of the Cu/SACZ/Al joints. When single ultrasonic was used in soldering, the interface IMC (Cu5Zn8) gradually thickens with the increase of ultrasonic degree. It is observed that the proportion of Zn or ZnO areas in solders decreases, and the proportion of Cu–Zn compound areas increases with the variation of ultrasonic degree. The maximum shear strength of joint reaches 46.01 MPa when the dual ultrasonic degree is 60°. The fracture position of the joint gradually shifts from the Al side interface to the solders and then to the Cu side interface. Originality/value The mechanism of ultrasonic action on micro-nanoparticles is further studied. By using different ultrasonic loading degrees to realize Cu/Al soldering, it is believed that the understandings gained in this study may offer some new insights for the development of low-temperature soldering methodology for heterogeneous materials.