Author
E. Vrancken
Bio: E. Vrancken is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Electron mobility & Passivation. The author has an hindex of 5, co-authored 7 publications receiving 441 citations.
Papers
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TL;DR: In this article, thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers.
Abstract: 7cm 2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2 anneal for device performance is shown.
242 citations
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01 Jan 2008TL;DR: In this paper, a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA /mum @Vdd= -1V.
Abstract: We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.
90 citations
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TL;DR: In this paper, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.
Abstract: In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-? deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.
54 citations
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01 Jun 2006TL;DR: For the first time, an STI module is integrated in an advanced 70nm Ge-pFET technology allowing EOT scaling down to 0.85nm as mentioned in this paper, and the impact of this aggressive scaling on hole mobility is also investigated by temperature measurements.
Abstract: For the first time, an STI module is integrated in an advanced 70nm Ge-pFET technology allowing EOT scaling down to 0.85nm. Gate leakage is kept below 0.2A/cm2 and ION is increased inversely proportional to the EOT. The impact of this aggressive EOT scaling on hole mobility is also investigated by temperature measurements down to 4K, suggesting the presence of defects at different levels of the Si/SiO 2 /HfO 2 gate stack.
47 citations
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TL;DR: Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology as mentioned in this paper, which is designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects.
Abstract: Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices The important role of pocket implants in degrading the drive current is highlighted Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement
25 citations
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TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results
558 citations
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TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
453 citations
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TL;DR: In this paper, surface analytical studies of interface formation of organic semiconductors with different materials are reviewed, including metal-organic interface dipole formation, charge transfer, chemical reaction, energy level alignment, in-diffusion, quenching of luminescence and possible recovery of it.
Abstract: Surface and interface analytical studies have generated critical insight of the fundamental processes at interfaces involving organic semiconductors. I will review surface analytical studies of interface formation of organic semiconductors with different materials. Metal/organic interface is a focus of both device engineering and basic science, since it is a key factor in nearly all important aspects of device performances, including operation voltages, degradation, and efficiency. I will discuss metal–organic interface dipole formation, charge transfer, chemical reaction, energy level alignment, in-diffusion, quenching of luminescence and possible recovery of it. The effect of the insertion of ultra-thin interlayers such as LiF and doping by alkali metals will also be discussed. In organic/organic interface, the energy offset between the two dissimilar organic materials is vitally important to efficient device operation of organic light emitting diodes (OLED), as well as change separation at donor–acceptor interface in organic photovoltaic devices (OPV). I will discuss the interface energy level alignment, band bending, Debye screening, and charge separation dynamics as observed in surface analytical studies, and the implications to OLED and OPV. The interfaces of OSCs with other inorganic materials are also important. For organic thin film transistors (OTFT), the electronic properties of the interface formed between the organic and the dielectric strongly influences the current–voltage characteristics, as the electronic activity has been shown to occur primarily at the interface between the dielectric and the organic materials. I will review the interface formation of OSCs with dielectric materials and with indium-tin-oxide (ITO), a material whose transparency and conductivity make it indispensable for a number of opto-electronic applications and whose electronic properties and energy level alignment with organics have proven dramatically altered by surface treatments.
218 citations
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TL;DR: In this paper, the transition from an indirect to a fundamental direct bandgap material will be discussed, and the most commonly used approaches, i.e., molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), will be reviewed in terms of crucial process parameters, structural as well as optical quality and employed precursor combinations including Germanium hydrides, Silicon hydride and a variety of Sn compounds like SnD4, SnCl4 or C6H5SnD3.
193 citations
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TL;DR: In this article, an ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al 2O3 layer between Hf2 and Ge, resulting in a low interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface.
Abstract: An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.
183 citations