E
Ed Grochowski
Researcher at Intel
Publications - 13
Citations - 1208
Ed Grochowski is an academic researcher from Intel. The author has contributed to research in topics: Multi-core processor & Amdahl's law. The author has an hindex of 7, co-authored 13 publications receiving 1206 citations.
Papers
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Journal ArticleDOI
Larrabee: a many-core x86 architecture for visual computing
Larry D. Seiler,Doug Carmean,Eric Sprangle,Tom Forsyth,Michael Abrash,Pradeep Dubey,Stephen Junkins,Adam T. Lake,Jeremy Sugerman,Robert Dale Cavin,Roger Espasa,Ed Grochowski,Toni Juan,Pat Hanrahan +13 more
TL;DR: This article consists of a collection of slides from the author's conference presentation, some of the topics discussed include: architecture convergence; Larrabee architecture; and graphics pipeline.
Journal ArticleDOI
Mitigating Amdahl's Law through EPI Throttling
TL;DR: This paper evaluates the performance benefits of an EPI throttle on an asymmetric multiprocessor (AMP) prototyped from a physical 4-way Xeon SMP server, and makes a compelling case for varying the amount of energy expended to process instructions according to theamount of available parallelism.
Patent
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
Hong Wang,John Paul Shen,Ed Grochowski,James P. Held,Bryant Bigbee,Shivnandan Kaushik,Gautham N. Chinya,Xiang Zou,Per Hammarlund,Xinmin Tian,Anil Aggarwal,Scott D. Rodgers,Prashant Sethi,Baiju V. Patel,Richard A. Hankins +14 more
TL;DR: In this paper, a method for managing user-level threads on a first instruction sequencer in response to executing user level instructions on a second instruction sequencers that is under control of an application level program is presented.
Patent
Load balancing for multi-threaded applications via asymmetric power throttling
Ryan Rakvic,Richard A. Hankins,Ed Grochowski,Hong Wang,Murali Annavaram,David K. Poulsen,Sanjiv Shah,John Paul Shen,Gautham N. Chinya +8 more
TL;DR: In this article, a first execution time of a first thread executing on a first processing unit of a multiprocessor is determined, the first and second threads executing in parallel.
Journal ArticleDOI
Improving the energy efficiency of big cores
Kenneth Czechowski,Victor W. Lee,Ed Grochowski,Ronny Ronen,Ronak Singhal,Richard Vuduc,Pradeep Dubey +6 more
TL;DR: Real-world examples of how architectural innovations can mitigate inefficiencies associated with “Big Cores” are provided -for example, micro-op caches obviate the costly decode of complex x86 instructions- resulting in a core architecture that is both high performance and energy efficient.