H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.

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Video coding with H.264/AVC: tools, performance, and complexity

The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.

A decade of reconfigurable computing: a visionary retrospective

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

/pdf/system-level-power-optimization-techniques-and-tools-58sern1xgm.pdf

System-level power optimization: techniques and tools

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.

Data and memory optimization techniques for embedded systems

Until the late eighties, information processing was associated with large mainframe computers and huge tape drives. During the nineties, this trend shifted towards information processing with personal computers, or PCs. The trend towards miniaturization continues. In the future, most of the information processing systems will be quite small and embedded into larger products such as transportation and fabrication equipment. Hence, these kinds of systems are called embedded systems. It is expected that the total market volume of embedded systems will be significantly larger than that of traditional information processing systems such as PCs and mainframes. Embedded systems share a number of common characteristics. For example, they must be dependable, efficient, meet real-time constraints and require customized user interfaces (instead of generic keyboard and mouse interfaces). Therefore, it makes sense to consider common principles of embedded system design. Embedded System Design starts with an introduction into the area and a survey of specification languages for embedded systems.A brief overview is provided of hardware devices used for embedded systems and also presents the essentials of software design for embedded systems. Real-time operating systems and real-time scheduling are covered briefly.Techniques for implementing embedded systems are also discussed, using hardware/software codesign. It closes with a survey on validation techniques. Embedded System Designcan be used as a text book for courses on embedded systems and as a source which provides pointers to relevant material in the area for PhD students and teachers. The book assumes a basic knowledge of information processing hardware and software.

Embedded System Design

From the Publisher:
This book grants the reader a comprehensive overview of the state-of-the-art in system-level memory management (data transfer and storage) related issues for complex data-dominated real-time signal and data processing applications. The authors introduce their own system-level data transfer and storage exploration methodology for data-dominated video applications. This methodology tackles the power and area reduction cost components in the architecture for this target domain, namely the system-level busses and the background memories. For the most critical tasks in the methodology, prototype tools have been developed to reduce the design time. To the researcher the book will serve as an excellent reference source, both for the overall description of the methodology and for the detailed descriptions of the system-level methodologies and synthesis techniques and algorithms. To the design engineers and CAD managers it offers an invaluable insight into the anticipated evolution of commercially available design tools as well as allowing them to utilize the book's concepts in their own research and development.

Custom Memory Management Methodology : Exploration of Memory Organisation for Embedded Multimedia System Design

Custom Memory Management Methodology

In this paper, we present novel strategies that are capable of significantly reducing the required memory sizes for a large class of data-intensive multimedia applications. The size reduction is obtained by reusing memory locations for arrays as much as possible through optimization of the storage order. These strategies are equally well suited for parallel and mono-processing applications, and are particularly useful in an embedded application context, where memory size is usually one of the main cost factors. Their feasibility and effectiveness is demonstrated by experimental results for some real-life multimedia applications, for which a considerable size reduction has been obtained.

Memory size reduction through storage order optimization for embedded parallel multimedia applications

A virtual camera system comprises a plurality of physical cameras and a hardware setup miming software to create virtual viewpoints for the virtual camera system. The position of the physical cameras is constrained, where the main constraint is the overlap between the physical cameras. The present invention provides a method for creating a virtual viewpoint of a plurality of images captured by the plurality of cameras, the images comprising current frames and previous frames. The method comprises creating background frames by combining a set of previous frames; creating a plurality of foreground masks by performing segmentation on the plurality of current frames, the segmentation comprising separating foreground objects from background objects using the created background frames; extracting the foreground objects by AND-ing the plurality of current frames with the created plurality of foreground masks; rendering the foreground objects by using a three dimensional depth-box constrained viewpoint interpolation algorithm on the plurality of current frames, the three dimensional depth box being constructed for each foreground object by exploiting information from the created foreground masks and positioning information of the foreground objects; rendering a view-dependent background image by performing homographic transformations on the created background frames; and creating the virtual viewpoint by superimposing the rendered foreground objects on the rendered background frame.

Virtual Camera System

This paper presents a radar and camera sensor fusion framework as a vulnerable road user (VRU) perception system that can automatically detect, track and classify different targets on the road. The first module of the system performs a spatial-temporal alignment on a common plane of detections provided by the radar signal processing and video processing modules. The second module is dedicated to data association of the aligned detections. A centralized fusion algorithm takes the current aligned detection set (locations and labels) as inputs from both sensors and performs multi-object tracking with a joint probabilistic data association (JPDAF) algorithm underlying the Kalman filter. The proposed radar/camera fusion system is experimentally evaluated through multi-object tracking scenarios. The experimental results demonstrate its reliability and effectiveness compared to a single sensor system

Eddy De Greef

Papers

Custom Memory Management Methodology : Exploration of Memory Organisation for Embedded Multimedia System Design

Custom Memory Management Methodology

Memory size reduction through storage order optimization for embedded parallel multimedia applications

Virtual Camera System

Radar-camera Fusion for Road Target Classification