E
Eli Bozorgzadeh
Researcher at University of California, Irvine
Publications - 44
Citations - 605
Eli Bozorgzadeh is an academic researcher from University of California, Irvine. The author has contributed to research in topics: Control reconfiguration & Scheduling (computing). The author has an hindex of 12, co-authored 44 publications receiving 560 citations.
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Journal ArticleDOI
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration
TL;DR: This work presents an exact approach for hardware-software (HW-SW) partitioning that guarantees correctness of implementation by considering placement implications as an integral aspect of HW-SW partitioning and presents a physically aware HW- SW partitioning heuristic that simultaneously partitions, schedules, and does linear placement of tasks on such devices.
Journal ArticleDOI
ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs
TL;DR: A routability-driven clustering method for cluster-based FPGAs that packs LUTs into logic clusters while incorporating routability metrics into a cost function and integrates the routability model into a timing-driven packing algorithm.
Journal ArticleDOI
FABSYN: floorplan-aware bus architecture synthesis
TL;DR: This paper proposes an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design.
Proceedings ArticleDOI
HARP: hard-wired routing pattern FPGAs
TL;DR: This work proposes a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches and results in 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency.
Proceedings ArticleDOI
Single-event-upset (SEU) awareness in FPGA routing
S. Golshan,Eli Bozorgzadeh +1 more
TL;DR: A SEU-aware routing algorithm is presented that provides significant reduction in bridging faults caused by SEUs and in asymmetric SRAM FPGA using the authors' router average FIT (failure-in-time) rate is reduced by 36%.