The fifth edition of "Numerical Methods for Engineers" continues its tradition of excellence. Instructors love this text because it is a comprehensive text that is easy to teach from. Students love it because it is written for them--with great pedagogy and clear explanations and examples throughout. The text features a broad array of applications, including all engineering disciplines. The revision retains the successful pedagogy of the prior editions. Chapra and Canale's unique approach opens each part of the text with sections called Motivation, Mathematical Background, and Orientation, preparing the student for what is to come in a motivating and engaging manner. Each part closes with an Epilogue containing sections called Trade-Offs, Important Relationships and Formulas, and Advanced Methods and Additional References. Much more than a summary, the Epilogue deepens understanding of what has been learned and provides a peek into more advanced methods. Approximately 80% of the end-of-chapter problems are revised or new to this edition. The expanded breadth of engineering disciplines covered is especially evident in the problems, which now cover such areas as biotechnology and biomedical engineering. Users will find use of software packages, specifically MATLAB and Excel with VBA. This includes material on developing MATLAB m-files and VBA macros.

Numerical methods for engineers

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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FPGA Architecture: Survey and Challenges

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

International Symposium on Quality Electronic Design

This paper presents a two-step aging-aware methodology for Representative Critical Paths (RCPs) selection from a large number of Critical Paths (CPs) in programmable logic devices. First, nomination of CPs is based on delay, temperature, and lexicographic function of duty cycle and switching activity filtering, which are the major causes in Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) aging mechanisms. Secondly, RCPs will be selected based on Fan-out (FO) and physical location of Logic Blocks (LBs) along a CP to decrease aging propagation and sensor distribution fairness, respectively. We then present a sensor insertion algorithm that will be used during design placement to avoid sensors inaccuracy. Implementation steps of sensor insertion are performed automatically with a limited human interaction. Higher aging-rate of RCPs than unselected CPs in our experiments demonstrates the effectiveness of the proposed methodology.

Path selection and sensor insertion flow for age monitoring in FPGAs

Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks.

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Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Renewable energy technology is a viable and promising solution toward achieving self-sustainable low power wireless sensor networks. However, the uncertainty and fluctuations in energy availability require a sophisticated energy management scheme, i.e., energy demand of each sensor node at any time does not exceed its available energy. In this paper, we propose to continuously adapt the energy requirements of sensor nodes based on availability of renewable energy sources, network routing needs and application quality constraints - addressing these trade-offs is our distinctive contribution in this paper. We present a novel algorithm to find the optimal uniform data quality for approximated data collection in a multihop energy-harvesting wireless sensor network (EH-WSN). Our approach guarantees routing sustainability in the network and has significantly less failed data queries (<;2%) as compared to a state-of-the-art energy-harvesting-aware routing protocol [10][11] which is not aware of data quality.

Adapting data quality with multihop routing for energy harvesting wireless sensor networks

Although Triple Modular Redundancy (TMR) has been widely used to mitigate single event upsets (SEUs) in SRAM-based FPGAs, SEU-caused bridging faults between the TMR modules do not guarantee correctness of TMR design under SEU. In this paper, we present a novel approximation algorithm for resource binding on scheduled datapaths at the presence of TMR, which aims at containment of each SEU within a single replica of tripled operations. The key challenges are to avoid resource sharing between modular redundant operations and also to reduce the possibility of TMR masking breaches in resource allocation. We introduce the notion of vulnerability gap during resource sharing to potentially reduce the effort for white space allocation at the physical design stage in order to avoid bridging faults between TMR resources. The experimental results show that our proposed resource binding algorithm, followed by floorplanner, reduces the potential of TMR breaches by 20%, on average.

SEU-aware resource binding for modular redundancy based designs on FPGAs

In heterogeneous architectures, FPGAs are not only expected to provide higher performance, but also to provide a more energy efficient solution for computationally intensive tasks. While parallelism and pipelining enhance performance on FPGA platforms, the data transfer rate from/to off-chip memory can cause performance degradation. We propose an automated high-level synthesis framework for FPGA-based acceleration of nested loops on large multidimensional input data sets. Given the high-level of parallelism in such applications, our proposed data prefetching algorithm determines the data rate for each parallel datapath. The empirical results on a case study in scientific computing show that FPGA mapping of such nested loops accelerates the application compared to traditional mapping on multicores. The FPGA-accelerated computation results in 3x speedup in runtime and 27x energy-delay-product savings compared to multicore computation.

Eli Bozorgzadeh

Papers

Path selection and sensor insertion flow for age monitoring in FPGAs

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Adapting data quality with multihop routing for energy harvesting wireless sensor networks

SEU-aware resource binding for modular redundancy based designs on FPGAs

Data-rate-aware FPGA-based acceleration framework for streaming applications