Eli Bozorgzadeh

Bio: Eli Bozorgzadeh is an academic researcher from University of California, Irvine. The author has contributed to research in topics: Control reconfiguration & Scheduling (computing). The author has an hindex of 12, co-authored 44 publications receiving 560 citations.

Modeling and control battery aging in energy harvesting systems

Abstract: Energy storage is a fundamental component for the development of sustainable and environment-aware technologies. One of the critical challenges that needs to be overcome is preserving the State of Health (SoH) in energy harvesting systems, where bursty arrival of energy and load may severely degrade the battery. Tools from Markov process and Dynamic Programming theory are becoming an increasingly popular choice to control dynamics of these systems due to their ability to seamlessly incorporate heterogeneous components and support a wide range of applications. Mapping aging rate measures to fit within the boundaries of these tools is non-trivial. In this paper, a framework for modeling and controlling the aging rate of batteries based on Markov process theory is presented. Numerical results illustrate the tradeoff between battery degradation and task completion delay enabled by the proposed framework.

Reconfiguration-Aware Task Graph Scheduling

Abstract: Due to increasing demand for reconfigurability in embedded systems, real-time task scheduling is challenged by non-negligible reconfiguration overheads. We introduce the problem of real-time task scheduling under reconfiguration overhead on heterogeneous reconfigurable systems while considering the data dependencies and data communication overhead. We introduce a novel graph representation which captures the delay overhead due to data dependencies and reconfiguration. We formulate the problem as a network flow problem and provide a mixed integer linear programming solution to minimize the completion time so called makespan. Results show that our proposed scheduling improves the makespan by 24.20% (on average) in comparison with maximum-transition-overhead scheduling.

UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation

Abstract: Despite all the available commercial and open-source frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators, sharing accelerators among multiple applications, and providing a nonblocking congestion-free environment for multiple applications to call multiple accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a non-blocking congestion-free environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations

Abstract: With advances in technology scaling, the configuration memory in SRAM-based FPGA is contributing a large portion of power consumption. Voltage scaling has been widely used to address the increases in power consumption in submicron regimes. However, with the advent of process variation in the configuration SRAMs, voltage scaling can undermine the integrity of a design implemented on the FPGA device as the design's functionality is determined by the contents of the configuration SRAMs. In this paper, we propose to exploit the abundance of homogenous resources on FPGA, in order to realize voltage scaling in the presence of process variation. Depending on the design to be implemented on FPGA, we select the minimal voltage that sustains a reliable placement. We then introduce a novel 2-phase placement algorithm that maximizes the reliability of the implemented design when voltage scaling is applied to the configuration memory. In the first phase, pre-deployment placement, we maximize the reliability of the implemented designs considering the a priori distribution of SRAM failures due to process variation and voltage scaling. The second phase, post-deployment placement, is performed once the device is fabricated in order to determine a fault-free placement of the design for the FPGA device. Our results indicate significant leakage power reduction (more than 50%) in the configuration memory when our placement technique is combined with voltage scaling with little delay degradation.

Statistical power profile correlation for realistic thermal estimation

Abstract: At system level, the on-chip temperature depends both on power density and the thermal coupling with the neighboring regions. The problem of finding the right set of input power profile(s) for accurate temperature estimation has not been studied. Considering only average or peak power density may lead either to underestimation or overestimation of the thermal crisis, respectively. To provide more realistic temperature estimation, we propose to incorporate multiple power profiles. Using the proposed statistical methods to determine the closeness between the power profiles, we apply a clustering algorithm to identify few input power profiles. We incorporate them in a thermal-aware floorplanner and empirical results show that using the single input power profile (average or peak) leads to 37% degradation in critical wire delay and 20% degradation in wire length, compared to using the multiple input power profiles.

Numerical methods for engineers

Abstract: The fifth edition of "Numerical Methods for Engineers" continues its tradition of excellence. Instructors love this text because it is a comprehensive text that is easy to teach from. Students love it because it is written for them--with great pedagogy and clear explanations and examples throughout. The text features a broad array of applications, including all engineering disciplines. The revision retains the successful pedagogy of the prior editions. Chapra and Canale's unique approach opens each part of the text with sections called Motivation, Mathematical Background, and Orientation, preparing the student for what is to come in a motivating and engaging manner. Each part closes with an Epilogue containing sections called Trade-Offs, Important Relationships and Formulas, and Advanced Methods and Additional References. Much more than a summary, the Epilogue deepens understanding of what has been learned and provides a peek into more advanced methods. Approximately 80% of the end-of-chapter problems are revised or new to this edition. The expanded breadth of engineering disciplines covered is especially evident in the problems, which now cover such areas as biotechnology and biomedical engineering. Users will find use of software packages, specifically MATLAB and Excel with VBA. This includes material on developing MATLAB m-files and VBA macros.

FPGA Architecture: Survey and Challenges

Abstract: Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

On-Chip Communication Architectures: System on Chip Interconnect

Abstract: Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. KEY FEATURES * A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends * Detailed analysis of all popular standards for on-chip communication architectures * Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts * Future trends that with have a significant impact on research and design of communication architectures over the next several years