The fifth edition of "Numerical Methods for Engineers" continues its tradition of excellence. Instructors love this text because it is a comprehensive text that is easy to teach from. Students love it because it is written for them--with great pedagogy and clear explanations and examples throughout. The text features a broad array of applications, including all engineering disciplines. The revision retains the successful pedagogy of the prior editions. Chapra and Canale's unique approach opens each part of the text with sections called Motivation, Mathematical Background, and Orientation, preparing the student for what is to come in a motivating and engaging manner. Each part closes with an Epilogue containing sections called Trade-Offs, Important Relationships and Formulas, and Advanced Methods and Additional References. Much more than a summary, the Epilogue deepens understanding of what has been learned and provides a peek into more advanced methods. Approximately 80% of the end-of-chapter problems are revised or new to this edition. The expanded breadth of engineering disciplines covered is especially evident in the problems, which now cover such areas as biotechnology and biomedical engineering. Users will find use of software packages, specifically MATLAB and Excel with VBA. This includes material on developing MATLAB m-files and VBA macros.

Numerical methods for engineers

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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FPGA Architecture: Survey and Challenges

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

International Symposium on Quality Electronic Design

Weakly hard real-time model has been successfully used for scheduling in firm real-time systems where some deadline misses are tolerable The tolerable deadline misses are specified using a (m, k) tuple, which means that tasks are desired to meet m deadlines in any k consecutive task invocations This model is adopted to provide QoS in many applications such as control systems or multimedia applications In this paper, we show that multiple QoS levels can be provided using (m, k) constraint with variable window size k Even though the size of window k is changed at run time, it is shown that the QoS level with minimum ratio of m/k is guaranteed for evenly distributed pattern Using this guarantee, we show that higher utilization with equal or higher QoS can be achieved in overload management

Multi-level QoS Support with Variable Window Size in Weakly Hard Real-Time Systems

Dynamic voltage/frequency scaling (DVFS) and adaptive body biasing (ABB) have shown to effectively reduce dynamic and leakage energy consumption in real-time embedded systems. Although these techniques exploit the slack time on a given task ordering, the task ordering may not provide a slack time distribution that DVFS/ABB can benefit from and this can limit the potential energy saving such techniques can provide. In this paper, we present an optimal network flow based solution for simultaneous static real-time scheduling and energy minimization (DVFS and ABB) on multiprocessors. Results show that our optimal solution reduces the energy dissipation by 47.84%, 26.21% and 17.46%, on average, in comparison with no-DVFS execution, voltage scaling algorithm with virtual continuous speed [1] and an optimal energy minimization algorithm without task re-ordering [2], respectively.

Unified theory of real-time task scheduling and dynamic voltage/frequency scaling on MPSoCs

Solar-powered embedded systems are challenged by variations and uncertainties in energy availability due to seasonal changes and weather conditions. Such systems need to deploy various schemes to adapt their energy consumption in order to achieve energy sustainability. We target solar-powered real-time systems with adaptive QoS model. A holistic middleware framework for energy management that orchestrates DVFS and application QoS in solar-powered real-time systems is proposed. Extensive experiments are carried out to show the effectiveness and the robustness of our technique on two case studies on a solar-powered smart camera system. Simulation results show an improvement of 19%–50% in terms of total QoS compared to a DVFS framework with fixed QoS model for real time embedded systems.

Harvesting-aware adaptive energy management in solar-powered embedded systems

Design variability due to within-die and die-to-die variations has potential to significantly increase the maximum operating clock period and the leakage power of the system in future process technology generations. When minimizing total energy of an MPSoC system, the variations in both the clock period and the leakage power of the multiple cores have to be taken into account. This paper targets system level task allocation to stochastically minimize the total energy of the system running multiple applications on MPSoC under process variation. In this work, we first introduce an integrated model for the total energy of the system which incorporates all the factors — dynamic energy, variations in leakage energy and variations in clock frequency. Our model shows very close correlation with the energy of the system computed using empirical methods. The proposed energy model enables efficient computation in the task allocation tools without requiring highly expensive stochastic analysis. We apply this model in allocating tasks in the embedded system benchmark suites on MPSoC. In addition, we propose a technique for allocating tasks that maximizes the energy yield of the system over an interval of energy constraints rather than a single energy constraint. In our experiments, we show that using our technique, we improve the average yield of the system significantly. Our experiments show that we can reach up to 5.3 times improvement in average yield of the energy constraints which translates into 0.6 increase in yield of the energy constraints on average.

Process variation aware system-level load assignment for total energy minimization using stochastic ordering

Despite all the available commercial and open-source frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators for a single application, sharing accelerators among multiple applications, and providing a non-blocking congestion-free environment for applications to invoke the accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a non-blocking congestion-free environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.

Eli Bozorgzadeh

Papers

Multi-level QoS Support with Variable Window Size in Weakly Hard Real-Time Systems

Unified theory of real-time task scheduling and dynamic voltage/frequency scaling on MPSoCs

Harvesting-aware adaptive energy management in solar-powered embedded systems

Process variation aware system-level load assignment for total energy minimization using stochastic ordering

UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation