Statistics--with confidence?

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

http://venividiwiki.ee.virginia.edu/mediawiki/images/c/c2/A_abidi.pdf

Phase Noise and Jitter in CMOS Ring Oscillators

A harmonic oscillator topology displaying an improved phase noise performance is introduced in this paper. Exploiting the advantages yielded by operating the core transistors in class-C, a theoretical 3.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator is achieved for the same current consumption. Further benefits derive from the natural rejection of the tail bias current noise, and from the absence of parasitic nodes sensitive to stray capacitances. Closed-form phase-noise equations obtained from a rigorous time-variant circuit analysis are presented, as well as a time-variant study of the stability of the oscillation amplitude, resulting in simple guidelines for a reliable design. Furthermore, the analysis of phase noise is extended to encompass a general harmonic oscillator, showing that all phase noise relations previously obtained for specific LC oscillator topologies are special cases of a very general and remarkably simple result.

Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results A prototype for the QVCO was implemented in a 035-/spl mu/m CMOS process with three standard metal layers The QVCO could be tuned between 164 and 197 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply The equivalent phase error between I and Q signals was at most 025/spl deg/

/pdf/analysis-and-design-of-a-1-8-ghz-cmos-lc-quadrature-vco-3tacbqcgff.pdf

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed.

/pdf/a-filtering-technique-to-lower-lc-oscillator-phase-noise-3q17r3raqh.pdf

A filtering technique to lower LC oscillator phase noise

A simple analysis relates the small-signal specification of a varactor's capacitance to an oscillator's tuning curve. The notion of an effective capacitance across the amplitude of oscillation is introduced. The analysis also explains how the varactor converts AM noise on the oscillation into FM, which is phase noise. The analysis is experimentally validated.

Varactor characteristics, oscillator tuning curves, and AM-FM conversion

The designer's guide to high-purity oscillators

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S11 below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs

A Low-Power Wideband CMOS LNA for WiMAX

This paper describes the design and implementation of a wideband merged LNA and mixer chip covering the frequency range from 0.1 to 3.85 GHz using 90-nm CMOS technology. Its high level of integration as well as its low power consumption makes it suitable for the rapidly growing software defined radio RF receivers. The chip performance achieves S11 below -10 dB along the entire band and a minimum single side band noise figure of 8.4 dB at IF frequency of 70 MHz. Power conversion gain is measured to be 12.1 dB while the input referred 1 dB compression point is measured to be -12.8 dBm. The chip core consumes only 9.8 mW from a 1.2 V supply with a die area, including the pads, of 0.88 mm2

Emad Hegazi

Papers

A filtering technique to lower LC oscillator phase noise

Varactor characteristics, oscillator tuning curves, and AM-FM conversion

The designer's guide to high-purity oscillators

A Low-Power Wideband CMOS LNA for WiMAX

A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation