Emmanuel Pistono

Bio: Emmanuel Pistono is an academic researcher from University of Grenoble. The author has contributed to research in topics: Return loss & Insertion loss. The author has an hindex of 14, co-authored 79 publications receiving 844 citations. Previous affiliations of Emmanuel Pistono include University of Savoy & Los Angeles Harbor College.

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

Abstract: This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

Slow-Wave Substrate Integrated Waveguide

Abstract: This paper describes a new concept of substrate integrated waveguide (SIW): a slow-wave substrate integrated waveguide (SW-SIW). Compared to a conventional SIW, the proposed topology requires a double-layer substrate with a bottom layer including internal metallized via-holes connected to the bottom conductive plane. The slow-wave effect is obtained by the physical separation of electric and magnetic fields in the structure. Electromagnetic simulations show that this topology of SIW allows decreasing the longitudinal dimension by more than 40% since the phase velocity is significantly smaller than that of a classical SIW. Simultaneously, the lateral dimension of the waveguide is also reduced. By considering a double-layer technology, SW-SIWs exhibiting a cutoff frequency of 9.3 GHz were designed, fabricated, and measured. The transversal dimension and the phase velocity of the proposed SW-SIW are both reduced by 40% as compared to a classical SIW designed for the same cutoff frequency, leading to a significant surface reduction. Moreover, an original kind of taper is proposed to achieve a good return loss when the SW-SIW is fed by a microstrip transmission line.

A Lossy Circuit Model Based on Physical Interpretation for Integrated Shielded Slow-Wave CMOS Coplanar Waveguide Structures

Abstract: This paper presents a new physical model for shielded slow-wave coplanar waveguide structures. This lossy electrical model is based on physical behavior of the transmission lines. It allows a better understanding of the losses distribution along the structure. The ohmic losses in the coplanar strips, as well as the ohmic losses and the eddy current losses in the floating shield strips are studied for transmission lines having different geometrical dimensions and hence electrical characteristics. The model is then validated on different CMOS technologies and leads to the efficient optimization of the slow-wave transmission lines, especially concerning the floating shield dimensions.

Compact and Broadband Millimeter-Wave Electrically Tunable Phase Shifter Combining Slow-Wave Effect With Liquid Crystal Technology

Abstract: Based on a CMOS slow-wave coplanar-waveguide transmission-line topology, a novel compact millimeter-wave phase shifter is presented. The tunability is accomplished by using a liquid crystal (LC) material as a tunable dielectric between the coplanar signal strip and the shielding plane of the slow-wave transmission line. The device tunability is considerably enhanced by moving the free-standing signal strip with the application of a bias voltage. Combining the miniaturizing benefits of the slow-wave effect with the continuous tuning of LC material, the proposed device occupies only 0.38 mm2 and exhibits high performance. The phase shifter was characterized up to 45 GHz for a maximum bias voltage of 20 V without significant power consumption. The reproducible measurements show a figure-of-merit (ratio between the maximum phase shift and the maximum insertion loss) of 51°/dB at 45 GHz.

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $\mu$ m CMOS Process

Abstract: In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 μm CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Abstract: Hybrid analog/digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Abstract: Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Reconfigurable and Tunable Metamaterials: A Review of the Theory and Applications

Abstract: Metamaterials are being applied to the development and construction of many new devices throughout the electromagnetic spectrum. Limitations posed by the metamaterial operational bandwidth and losses can be effectively mitigated through the incorporation of tunable elements into the metamaterial devices. There are a wide range of approaches that have been advanced in the literature for adding reconfiguration to metamaterial devices all the way from the RF through the optical regimes, but some techniques are useful only for certain wavelength bands. A range of tuning techniques span from active circuit elements introduced into the resonant conductive metamaterial geometries to constituent materials that change electromagnetic properties under specific environmental stimuli. This paper presents a survey of the development of reconfigurable and tunable metamaterial technology as well as of the applications where such capabilities are valuable.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

Abstract: This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.