This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.

/pdf/hotspot-a-compact-thermal-modeling-methodology-for-early-43x1muqtv2.pdf

HotSpot: a compact thermal modeling methodology for early-stage VLSI design

Security of a computer system has been traditionally related to the security of the software or the information being processed. The underlying hardware used for information processing has been considered trusted. The emergence of hardware Trojan attacks violates this root of trust. These attacks, in the form of malicious modifications of electronic hardware at different stages of its life cycle, pose major security concerns in the electronics industry. An adversary can mount such an attack with an objective to cause operational failure or to leak secret information from inside a chip-e.g., the key in a cryptographic chip, during field operation. Global economic trend that encourages increased reliance on untrusted entities in the hardware design and fabrication process is rapidly enhancing the vulnerability to such attacks. In this paper, we analyze the threat of hardware Trojan attacks; present attack models, types, and scenarios; discuss different forms of protection approaches, both proactive and reactive; and describe emerging attack modes, defenses, and future research pathways.

Hardware Trojan Attacks: Threat Analysis and Countermeasures

Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.

High-performance CMOS variability in the 65-nm regime and beyond

This new edition includes more than 107,000 terms and definitions, more than 5,000 new to this edition. More than 45 consultants from all the major medical and health science specialties have reviewed each word for accuracy and clarity, including new consultants for the specialties of endocrinology, gastroenterology, geriatrics, and rheumatology. The art program has also been extensively enhanced and now includes approximately 1,500 images and illustrations.

Stedman's Medical Dictionary

GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a challenge for programmers. Furthermore, optimizing for power consumption is even more difficult. Unfortunately, as a result of the high number of processors, the power consumption of many-core processors such as GPUs has increased significantly. Hence, in this paper, we propose an integrated power and performance (IPP) prediction model for a GPU architecture to predict the optimal number of active processors for a given application. The basic intuition is that when an application reaches the peak memory bandwidth, using more cores does not result in performance improvement. We develop an empirical power model for the GPU. Unlike most previous models, which require measured execution times, hardware performance counters, or architectural simulations, IPP predicts execution times to calculate dynamic power events. We then use the outcome of IPP to control the number of running cores. We also model the increases in power consumption that resulted from the increases in temperature. With the predicted optimal number of active cores, we show that we can save up to 22.09%of runtime GPU energy consumption and on average 10.99% of that for the five memory bandwidth-limited benchmarks.

https://www.cc.gatech.edu/~hyesoon/hong_isca10.pdf

An integrated GPU power and performance model

Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

/pdf/full-chip-leakage-estimation-considering-power-supply-and-4am1rf1wjw.pdf

Full chip leakage-estimation considering power supply and temperature variations

The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we scale toward 10 nm technologies, this problem will only worsen. New circuit families and design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new models of performance which accurately capture the manufacturing realities. Recently, one step toward this goal was made via a new variational reduced order interconnect model that efficiently captures large scale fluctuations in global parameter values. Using variational calculus the linear interconnect systems are represented by analytical models that include the global variational parameters explicitly. In this work we present a framework which extends the previous work to a linear-centric simulation methodology with accurate nonlinear device models and their fluctuations. The framework is applied to generate path delay distributions under nonlinear and linear parameter fluctuations.

/pdf/a-linear-centric-simulation-framework-for-parametric-4jdposm296.pdf

A Linear-Centric Simulation Framework for Parametric Fluctuations

Recently a probability interpretation of moments was proposed as a compromise between the Elmore delay and higher order moment matching for RC timing estimation (Kay and Pileggi, 1998). By modeling RC impulses as time-shifted incomplete gamma distribution function, the delays could be obtained via table lookup using a gamma integral table and the first three moments of the impulse response. However, while this approximation works well for many examples, it struggles with responses when the metal resistance becomes dominant, and produces results with impractical time shift values In this paper the probability interpretation is extended to the circuit homogeneous response, without requiring the time shift parameter. The gamma distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model (RC tree or mesh), the stability of the homogeneous-gamma distribution model is guaranteed. It is demonstrated that when a table model is carefully constructed, the h-gamma approximation provides for excellent improvement over the Elmore delay in terms of accuracy, with very little additional cost in terms of CPU time.

/pdf/h-gamma-an-rc-delay-metric-based-on-a-gamma-distribution-8jlxlxu55y.pdf

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response

Noise arising from line-to-line coupling is a major problem for deep submicron design, and present technology trends are causing an increase in this type of noise. Common current methods to decrease coupling noise include shielding and buffering, both of which can increase overall power dissipation. An alternative method is spacing, which has the added benefit of improving the manufacturability (i.e. defect insensitivity) of the design. This paper explores the issue of coupling noise reduction, and proposes performance metrics that can be used by the designer to determine which of the alternative methods is best suited for a specific interconnect configuration.

/pdf/optimal-shielding-spacing-metrics-for-low-power-design-5dyh0on9t1.pdf

Optimal shielding/spacing metrics for low power design

With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, making noise analysis and verification challenging in terms of both run time and memory. We propose a power grid reduction scheme based on algebraic multigrid principles, in which the coarser-level grid and the restriction operators are constructed automatically from the circuit matrices. This method is suitable for large-scale power grid transient and AC analysis. Experimental results show an order of magnitude speed up over flat analysis in addition to practical tradeoffs for accuracy, CPU time and memory usage.

/pdf/power-grid-reduction-based-on-algebraic-multigrid-principles-13u0fpkppn.pdf

Emrah Acar

Papers

Full chip leakage-estimation considering power supply and temperature variations

A Linear-Centric Simulation Framework for Parametric Fluctuations

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response

Optimal shielding/spacing metrics for low power design

Power grid reduction based on algebraic multigrid principles