Author
Ender Culha
Bio: Ender Culha is an academic researcher from Boğaziçi University. The author has contributed to research in topics: Field-programmable gate array & High-level synthesis. The author has co-authored 2 publications.
Papers
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05 Sep 2012
TL;DR: A synthesis framework that generates a formally verifiable RTL from a high level language using CDFGs from ANSI-C, LRH(+) and VHDL and guarantees detection of hardware redundancy and word-length mismatch related bugs by static code checking.
Abstract: This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57\% for delay and 3.76\% for area estimations. Our framework extracts CDFGs from ANSI-C, LRH(+) \cite{Kurumahmut2009} and VHDL. CDFGs are verified using the symbolic model checker NuSMV \cite{nusmv} with temporal logic properties. This method guarantees detection of hardware redundancy and word-length mismatch related bugs by static code checking.
18 Apr 2012
TL;DR: A high-level design-time verifiable Register-Transfer Level (RTL) generator which is integrated to RH(+) framework, a delay and area estimation model of the generated circuit for the Xilinx Spartan 3 FPGA Family is presented.
Abstract: Field Programmable Gate Arrays (FPGAs) provides fast and low cost implementation of DSP systems. The increasing popularity of FPGAs and lack of experience of the DSP algorithm designers on HDLs, makes the High Level Synthesis tools vital for design, early performance estimation, prototyping, testing and verification. In this paper, we present a high-level design-time verifiable Register-Transfer Level (RTL) generator which is integrated to RH(+) framework, a delay and area estimation model of the generated circuit for the Xilinx Spartan 3 FPGA Family.