Eric Beyne

Bio: Eric Beyne is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Wafer & Die (integrated circuit). The author has an hindex of 44, co-authored 626 publications receiving 9619 citations. Previous affiliations of Eric Beyne include IMEC & Siemens.

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Abstract: In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Method of fabrication of a microstructure having an internal cavity

Abstract: A method of fabricating a microstructure having an inside cavity The method includes depositing a first layer or a first stack of layers in a substantially closed geometric configuration on a first substrate Then, performing an indent on the first layer or on the top layer of said first stack of layers Then, depositing a second layer or a second stack of layers substantially with said substantially closed geometric configuration on a second substrate Then, aligning and bonding said first substrate on said second substrate such that a microstructure having a cavity is formed according to said closed geometry configuration

MEMS for wireless communications: 'from RF-MEMS components to RF-MEMS-SiP'

Abstract: Wireless communication has led to an explosive growth of emerging consumer and military applications of radio frequency (RF), microwave and millimeter wave circuits and systems. Future personal (hand-held) and ground communications systems as well as communications satellites necessitate the use of highly integrated RF front-ends, featuring small size, low weight, high performance and low cost. Continuing chip scaling has contributed to the extent that off-chip, bulky passive RF components, such as high-Q inductors, ceramic and SAW filters, varactor diodes and discrete PIN diode switches, have become limiting. Micro-machining or MEMS technology is now rapidly emerging as an enabling technology to yield a new generation of high-performance RF-MEMS passives to replace these off-chip passives in wireless communication (sub)systems. This paper reviews the progress in RF-MEMS from a device and integration perspective. The worldwide state-of-the-art of RF-MEMS devices including switches, variable capacitors, resonators and filters are described. Next, it is stipulated how integration of RF-MEMS passives with other passives (as inductors, LC filters, SAW devices, couplers and power dividers) and, active circuitry (ASICs, RFICs) can lead to the so-called RF-MEMS system-in-a-package (RF-MEMS-SiP) modules. The evolution of the RF-MEMS-SiP technology is illustrated using IMEC's microwave multi-layer thin-film MCM-D technology which today already serves as a technology platform for RF-SiP.

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Abstract: Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device

Abstract: The present invention provides a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of: forming the first planar substrate, attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer; attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer; partly curing the polymer adhesive layer, disconnecting the release layer from the first substrate to separate the first substrate from the camer, followed by coing the polymer adhesive layer.

Wearable Electronics and Smart Textiles: A Critical Review

Abstract: Electronic Textiles (e-textiles) are fabrics that feature electronics and interconnections woven into them, presenting physical flexibility and typical size that cannot be achieved with other existing electronic manufacturing techniques. Components and interconnections are intrinsic to the fabric and thus are less visible and not susceptible of becoming tangled or snagged by surrounding objects. E-textiles can also more easily adapt to fast changes in the computational and sensing requirements of any specific application, this one representing a useful feature for power management and context awareness. The vision behind wearable computing foresees future electronic systems to be an integral part of our everyday outfits. Such electronic devices have to meet special requirements concerning wearability. Wearable systems will be characterized by their ability to automatically recognize the activity and the behavioral status of their own user as well as of the situation around her/him, and to use this information to adjust the systems' configuration and functionality. This review focuses on recent advances in the field of Smart Textiles and pays particular attention to the materials and their manufacturing process. Each technique shows advantages and disadvantages and our aim is to highlight a possible trade-off between flexibility, ergonomics, low power consumption, integration and eventually autonomy.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Antenna design for UHF RFID tags: a review and a practical application

Abstract: In this paper, an overview of antenna design for passive radio frequency identification (RFID) tags is presented. We discuss various requirements of such designs, outline a generic design process including range measurement techniques and concentrate on one practical application: RFID tag for box tracking in warehouses. A loaded meander antenna design for this application is described and its various practical aspects such as sensitivity to fabrication process and box content are analyzed. Modeling and simulation results are also presented which are in good agreement with measurement data.

Three-dimensional battery architectures.

Abstract: The worldwide thirst for portable consumer electronics in the 1990s had an enormous impact on portable power. Lithium ion batteries, in which lithium ions shuttle between an insertion cathode (e.g., LiCoO2) and an insertion anode (e.g., carbon), emerged as the power source of choice for the highperformance rechargeable-battery market. The performance advantages were so significant that lithium ion batteries not only replaced Ni-Cd batteries but left the purported successor technology, nickel-metal hydride, in its wake.1 The thick metal plates of * To whom correspondence should be addressed. J.W.L: e-mail, jwlong@ccs.nrl.navy.mil; telephone, (+1)202-404-8697. B.D.: e-mail, bdunn@ucla.edu; telephone, (+1)310-825-1519. D.R.R.: e-mail, rolison@nrl.navy.mil; telephone, (+1)202-767-3617. H.S.W.: e-mail, white@chem.utah.edu; telephone, (+1)810-585-6256. † Naval Research Laboratory. ‡ UCLA. § University of Utah. 4463 Chem. Rev. 2004, 104, 4463−4492