Eric Gutierrez

Bio: Eric Gutierrez is an academic researcher from Carlos III Health Institute. The author has contributed to research in topics: Voltage-controlled oscillator & Ring oscillator. The author has an hindex of 7, co-authored 32 publications receiving 155 citations. Previous affiliations of Eric Gutierrez include Charles III University of Madrid & University of Waterloo.

A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

Abstract: In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order $\Delta \Sigma $ modulators. A first advantage of our approach is that it unveils systematic error components not described by the equivalence with a conventional $\Delta \Sigma $ modulator. A second advantage is that, by a proper selection of the pulses generated by the PFM, we can theoretically construct an open loop VCO-ADC with an arbitrary noise shaping order. Unfortunately, with the exception of the first-order noise shaping case, the required pulse waveforms cannot easily be implemented on the circuit level. However, we describe circuit techniques to achieve a good approximation of the required pulse waveforms, which can easily be implemented by practical circuits. Finally, our approach enables a straightforward description of multistage $\Delta \Sigma $ modulator architectures, which is an alternative and practically feasible way to realize a VCO-ADC with extended noise shaping.

SNDR Limits of Oscillator-Based Sensor Readout Circuits

Abstract: This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.

0.04-mm 2 103-dB-A Dynamic Range Second-Order VCO-Based Audio $\Sigma\Delta$ ADC in 0.13- $\mu$ m CMOS

Abstract: This paper presents a compact-area, low-power, highly digital analog-to-digital converter (ADC) for audio applications. The proposed converter is implemented using only oscillators and digital circuitry, without operational amplifiers nor other highly linear circuits. The ADC consists of two twin second-order $\Sigma \Delta $ modulators, which can work both individually or in a pseudodifferential configuration. The proposed system has been implemented in a 0.13- $\mu \text{m}$ standard CMOS technology. The single-ended configuration occupies an active area of 0.02 mm2, is powered at 1.8 V with a current consumption of 155 $\mu \text{A}$ , and achieves an A-weighted dynamic range (DR) of 98 dB-A. The pseudodifferential configuration achieves 103 dB-A of A-weighted DR at the expense of doubling the area and power consumption.

Analytical Evaluation of VCO-ADC Quantization Noise Spectrum Using Pulse Frequency Modulation

Abstract: Oversampled ADCs based on voltage-controlled oscillators have been analyzed using statistical models inherited from sigma-delta modulation. This letter shows that the discrete Fourier transform of a VCO-ADC output sequence can be calculated analytically for single tone inputs. The calculation is based on the transformation of the VCO output into a pulse frequency modulated signal that can be represented by a trigonometric series. Knowledge of the VCO-ADC output spectrum allows accurate evaluation of the SNDR dependence with the VCO oscillation frequency and gain constant. The SNDR predictions of the proposed model have been compared to behavioral simulations displaying only a deviation of 0.7 dB.

Frequency-encoded integrators applied to filtering and sigma-delta modulation

Abstract: A theoretical approach to the problem of replicating continuous-time systems with frequency modulated oscillators is proposed. It has been shown that continuous time filters and especially, the loop filter of a sigma-delta modulator, can be implemented with VCOs and digital circuitry. The analysis of these architectures is usually based on the integral relationship between frequency and phase in an oscillator. However, the spectrum of a modulated oscillator contains components at the harmonics of the oscillation frequency that cannot be easily described using the phase-frequency relationship. We propose a model in which a VCO is considered a signal encoder instead of an integrator. This model is applied then to the design of a band pass-sigma delta modulator.

A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping

Abstract: This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog-to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma–delta modulator (CT-SDM). The counter consists only of digital building blocks, and the VCOs are implemented using ring oscillators, which are also digital-friendly. No traditional analog blocks, such as opamps, OTAs, or comparators, are used. As a proof of concept, we have implemented a third-order VCO-based CT-SDM for a 10-MHz bandwidth in the low-power version of a 65-nm CMOS technology. This prototype shows a measured performance of 71/66.2/62.5-dB DR/SNR/SNDR at a 10-MHz bandwidth while consuming 1.8 mW from a 1.0-V analog and 1.9 mW from a 1.2-V digital supply. With digital calibration, the nonlinearity could be pushed below the noise level, leading to an improved peak SNDR of 66 dB.

A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

Abstract: In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order $\Delta \Sigma $ modulators. A first advantage of our approach is that it unveils systematic error components not described by the equivalence with a conventional $\Delta \Sigma $ modulator. A second advantage is that, by a proper selection of the pulses generated by the PFM, we can theoretically construct an open loop VCO-ADC with an arbitrary noise shaping order. Unfortunately, with the exception of the first-order noise shaping case, the required pulse waveforms cannot easily be implemented on the circuit level. However, we describe circuit techniques to achieve a good approximation of the required pulse waveforms, which can easily be implemented by practical circuits. Finally, our approach enables a straightforward description of multistage $\Delta \Sigma $ modulator architectures, which is an alternative and practically feasible way to realize a VCO-ADC with extended noise shaping.

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Abstract: The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs The shrinking supply voltage and presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance This article reviews the basic principles of time encoding applied, in particular, to analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs), one of the most successful time-encoding techniques to date

A Coarse-Fine VCO-ADC for MEMS Microphones With Sampling Synchronization by Data Scrambling

Abstract: This letter presents a mostly digital analog-to-digital converter implemented with voltage-controlled oscillators that can directly interface a capacitive MEMS microphone. The ADC is based on two ring oscillators and a coarse-fine counting circuitry. Coarse and fine counters are synchronized using a novel data scrambling technique to mitigate metastability and timing errors. This method enables a very low power consumption in the digital post-processing circuit. The proposed ADC, prototyped in 130-nm CMOS, achieves 73.8 dB-A of signal-to-noise and distortion ratio (SNDR) peak and 97 dB of dynamic range (DR) in a 20-kHz BW, while consuming 240 $\mu \text{W}$ from the 1.5-V/1.2-V power supplies. In a reduced power mode (8 kHz BW) with relaxed oscillation parameters, it reaches 66.4 dB-A of SNDR peak and 93 dB of DR with a power consumption of only 77 $\mu \text{W}$ .

SNDR Limits of Oscillator-Based Sensor Readout Circuits

Abstract: This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.