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Author

Eric Karl

Other affiliations: University of Michigan
Bio: Eric Karl is an academic researcher from Intel. The author has contributed to research in topics: Static random-access memory & CMOS. The author has an hindex of 20, co-authored 42 publications receiving 1759 citations. Previous affiliations of Eric Karl include University of Michigan.

Papers
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Proceedings ArticleDOI
01 Dec 2014
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Abstract: A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

558 citations

Proceedings ArticleDOI
03 Apr 2012
TL;DR: A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon to address process variation and fin quantization at 22nm.
Abstract: Future product applications demand increasing performance with reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM V MIN and low-voltage performance as technology scaling follows Moore's law to the 22nm node. A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon. Tri-gate technology reduces short-channel effects (SCE) and improves subthreshold slope to provide 37% improved device performance at 0.7V. Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply drive current. Process-circuit co-optimization of transient voltage collapse write assist (TVC-WA) and wordline underdrive read assist (WLUD-RA) features address process variation and fin quantization at 22nm and enable a 175mV reduction in the supply voltage required for 2GHz SRAM operation. Figure 13.1.1 shows an SEM top-down view of a 0.092μm2 high-density 6T SRAM bitcell (HDC) and a 0.108μm2 low-voltage 6T SRAM cell (LVC) after gate and diffusion processing. Computational OPC/RET techniques extend the capabilities of 193nm immersion lithography to allow a 1.85× increase in array density relative to 32nm designs [1].

177 citations

Proceedings ArticleDOI
01 Feb 2008
TL;DR: Two compact structures are introduced to digitally quantify the change in performance and power of devices undergoing NBTI and defect-induced oxide breakdown and are amenable to use in a standard-cell design with low area and power overhead.
Abstract: The NBTI sensor proposed is intended to be used for general NBTI characterization and not in- situ monitoring of degradation, due to large area overhead (~450x area of NBTI sensor in this work), inability to correct for temperature variations encountered during operation and the analog output of the sensor. We introduce two compact structures to digitally quantify the change in performance and power of devices undergoing NBTI and defect-induced oxide breakdown. The small size of the sensors makes them amenable to use in a standard-cell design with low area and power overhead. The sensors can be implemented in large numbers to collect data on degradation and statistical performance of the devices.

124 citations

Journal ArticleDOI
TL;DR: This article presents a broad vision of a new cohesive architecture, ElastIC, which can provide a pathway to successful design in unpredictable silicon and incorporates several novel concepts in these areas.
Abstract: ElastIC must deal with extremes a multiple core processor subjected to huge process variations, transistor degradations at varying rates, and device failures. In this article, we present a broad vision of a new cohesive architecture, ElastIC, which can provide a pathway to successful design in unpredictable silicon. ElastIC is based on aggressive run-time self-diagnosis, adaptivity, and self-healing. It incorporates several novel concepts in these areas and brings together research efforts from the device, circuit, testing, and microarchitecture domains. Architectures like ElastIC will become vital in extremely scaled CMOS technologies (such as 22 nm); ideally, they will target applications such as multimedia, Web services, and transaction processing

117 citations

Journal ArticleDOI
09 Nov 2010
TL;DR: An adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die is introduced.
Abstract: SRAM scaling faces increasing challenges in meeting power, performance, and density requirements as Moore's law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologies and conventional SRAM is no longer able to fully realize the benefits of scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. VCC scaling is especially important to meet increasingly stringent power constraints [1]. Circuit techniques proposed in recent years enable SRAM V CC scaling by expanding read and write margins [2–6]. However, the improved design margins for SRAM V CC scaling are often achieved with significant design overhead, e.g., additional power supply [4], increased circuit complexity [5], and testing overheads required for die-by-die programming [6].

83 citations


Cited by
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Journal ArticleDOI
20 Jan 2017-Science
TL;DR: High-performance top-gated carbon nanotube field-effect transistors with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale.
Abstract: High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

485 citations

Journal ArticleDOI
18 Jun 2016
TL;DR: The basic architecture of the Neurocube is presented and an analysis of the logic tier synthesized in 28nm and 15nm process technologies are presented and the performance is evaluated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.
Abstract: This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.

415 citations

Journal ArticleDOI
TL;DR: In this paper, a microarchitecture-aware model for process variation is proposed, including both random and systematic effects, and the model is specified using a small number of highly intuitive parameters.
Abstract: Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.

386 citations

Journal ArticleDOI
TL;DR: A systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures, carrier densities, and contact dimensions finds that Au deposited in ultra-high vacuum yields three times lower RC than under normal conditions.
Abstract: The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (1012 to 1013 cm–2), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (∼10–9 Torr) yields three times lower RC than under normal conditions, reaching 740 Ω·μm and specific contact resistivity 3 × 10–7 Ω·cm2, stable for over four months. Modeling reveals separate RC contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ∼35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the “14 nm” technology node.

369 citations

Journal ArticleDOI
01 Aug 2018
TL;DR: This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.
Abstract: In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

343 citations