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Erik Säll

Bio: Erik Säll is an academic researcher. The author has contributed to research in topics: Flash (photography) & Computer science. The author has an hindex of 1, co-authored 1 publications receiving 21 citations.

Papers
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01 Jan 2007
TL;DR: In this paper, a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation.
Abstract: A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluatio ...

21 citations

Proceedings ArticleDOI
19 Sep 2022
TL;DR: In this article , an integer-N bang-bang digital PLL for synthesis of a high purity clock targeting output frequencies of 12 and 16 GHz using a 500 MHz reference is presented.
Abstract: This paper presents an integer-N bang-bang digital PLL for synthesis of a high purity clock targeting output frequencies of 12 and 16 GHz using a 500 MHz reference. The PLL uses a self-resetting differential comparator-based BBPD with low hysteresis and a dual DCO architecture for lowest phase noise at respective output frequency. The PLL is implemented in a 7 nm FinFET process with an area of 0.18 mm2and achieves <40fs RMS jitter integrated between 1 kHz and 100MHz with a phase noise of -118.6 dBc/Hz at 1 MHz offset, while consuming 85.4 mW. The jitter varies less than 1.5dB across a -40 C to +85 C ambient temperature range.

Cited by
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Journal ArticleDOI
TL;DR: A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed, enabling power and hardware efficiency improvements.
Abstract: A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample ...

44 citations

Proceedings ArticleDOI
05 Jan 2009
TL;DR: A low power and variable resolution (adaptive) flash ADC that enables exponential power reduction while the reduction in resolution is linear is proposed.
Abstract: In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The ADC, capable of operating at 4-bit, 5-bit, and 6-bit precision, dissipates 6mW at 4-bit and 12mW at 6-bit, and operates at a sampling frequency of 1 to 2 GSPS. The ADC has been designed and simulated in standard 65nm CMOS technology using Cadence tools

33 citations

01 Jan 2008
TL;DR: The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters, for single- and multi-state DSP systems.
Abstract: The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multi ...

19 citations

01 Jan 2012
TL;DR: The main focus in this thesis is on the aspects related to the implementation of integer and non-integer sampling rate conversion (SRC).
Abstract: The main focus in this thesis is on the aspects related to the implementation of integer and non-integer sampling rate conversion (SRC). SRC is used in many communication and signal processing appl ...

14 citations

Proceedings ArticleDOI
24 Mar 2014
TL;DR: A 4-bit, 1.8 V, high speed, low power, and low voltage CMOS flash ADC for SoC applications has been proposed and the high speed and low power TIQ flash ADC architecture is designed and simulated using level 3 spice models.
Abstract: Analog-to-Digital converters (ADC) are useful components in signal processing and communication systems. In the digital signal processing (DSP) low power and low voltage are of prime concern and it is challenging to design high speed mixed signal circuits. This paper describes the ultra high speed ADC design using a 2×1 multiplexer based encoder that is highly suitable and accurate. Speed is an important parameter that is enhanced by using 2×1 multiplexer encoding network. In this paper a 4-bit, 1.8 V, high speed, low power, and low voltage CMOS flash ADC for SoC applications has been proposed. The 4-bit Flash type ADC has been designed with a step size of 0.038125 V. The proposed ADC architecture utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded Complementary Metal oxide semiconductor (CMOS) inverters as a comparator. The high speed and low power TIQ flash ADC architecture is designed and simulated using level 3 spice models. The ADC is designed with a 4 bit resolution and is simulated in 0.12 μm standard CMOS that offers a high data conversion rate of 4 Giga Samples/sec. Differential (DNL) errors measured are between -0.174 LSB to +0.256LSB. The ADC consumes 6.2031 mW from a 1.8 V supply with dynamic range of 600 mV.

13 citations