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Ethan Schuyler Long

Other affiliations: Portland State University
Bio: Ethan Schuyler Long is an academic researcher from University of Oslo. The author has contributed to research in topics: Thermal oxidation & Thin film. The author has an hindex of 6, co-authored 8 publications receiving 68 citations. Previous affiliations of Ethan Schuyler Long include Portland State University.

Papers
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Journal ArticleDOI
TL;DR: In this paper, the pile-up effect was shown to occur at the oxidation interface, with the highest germanium content occurring at the same interface, and the proposed models may be used in nanostructuring of thin films of SiGe by oxidation and in the design of coreshell structures and transistors.
Abstract: Several fundamental aspects of the oxidation-induced redistribution of Ge in thin films of SiGe are studied. This includes the incorporation of Ge into the oxide and the formation of what is alternatively referred to as pile-up, snow-plow, or a germanium-rich layer. Experimental data from the present work shows longer oxidation times leading to an increase of Ge content in the pile-up region and eventually creating a single high Ge content pile-up layer by entirely consuming the initial SiGe layer. The pile-up effect was shown to occur at the oxidation interface, with the highest Ge content occurring at the same interface. For a given oxide thickness, the redistribution of Ge and the formation of a pile-up region was shown experimentally to be independent of temperature in the range between 800 °C and 1000 °C. Simulations using common models for the oxidation of Si and diffusion of Si in SiGe indicate that temperature does have an influence on the composition of the pile-up layer, though the range of achievable compositions is limited. The flux of Si due to diffusion of Si in SiGe relative to the oxidation-induced flux of Si out of the SiGe is integral to the formation and dimensions of a pile-up region. Two predictive relations were derived for describing the dynamics of oxidation of SiGe. The first relation is given for determining the pile-up layer thickness as a function of oxide thickness and the composition of the pile-up layer. The second relation assumes a limited supply of Si and is for determination of the minimum initial thickness of a SiGe layer to avoid oxidation of Ge. The validity of these equations was confirmed experimentally by RBS and XPS data from the present work. The proposed models may be used in nanostructuring of thin films of SiGe by oxidation and in the design of core-shell structures and transistors. This is all done with a focus on oxidation of epitaxial thin films (< 100 nm) of Si1-XGeX in dry O2 at 1 atm between 800 °C and 1000 °C.

17 citations

Journal ArticleDOI
TL;DR: In this article, the authors describe the enhancement of Ge concentration in sub-100-nm thin films of SiGe by dry thermal oxidation and present a model for determination of the Ge content in the pile-up layer along with appropriate values for the activation energy and preexponential constant for diffusion of Si in Si1-XGeX.
Abstract: The data and analysis presented herein aims to facilitate the design and manufacture of SiGe based nanostructures and devices by describing the enhancement of Ge concentration in sub-100-nm thin films of SiGe by dry thermal oxidation. Thin films of SiGe were restructured by using thermal oxidation induced self-organization of Si and Ge atoms to create a layer of enhanced Ge concentration. The dry thermal oxidations were carried out at temperatures between 800 °C and 1000 °C. The influence of temperature on the Ge content at the oxidation front, as measured by x-ray diffraction, is examined and supported by simulation results. A model for determination of the Ge content in the pile-up layer is presented along with appropriate values for the activation energy and pre-exponential constant for diffusion of Si in Si1-XGeX. This model may also be used for determination of the diffusivity of Si in Si1-XGeX by fitting the model results to the measured Ge concentration in the pile-up layer. It is observed that the...

15 citations

01 Jan 2012
TL;DR: In this article, two predictive relations for describing the dynamics of oxidation of SiGe were derived for determining the pile-up layerthickness as a function of oxide thickness and the composition of the initial SiGe layer.
Abstract: (Received 29 August 2011; accepted 15 December 2011; published online 24 January 2012)Several fundamental aspects of the oxidation-induced redistribution of Ge in thin films of SiGe arestudied. This includes the incorporation of Ge into the oxide and the formation of what isalternatively referred to as pile-up, snow-plow, or a germanium-rich layer. Experimental data fromthe present work shows longer oxidation times leading to an increase of Ge content in the pile-upregion and eventually creating a single high Ge content pile-up layer by entirely consuming theinitial SiGe layer. The pile-up effect was shown to occur at the oxidation interface, with the highestGe content occurring at the same interface. For a given oxide thickness, the redistribution of Geand the formation of a pile-up region was shown experimentally to be independent of temperaturein the range between 800 C and 1000 C. Simulations using common models for the oxidation ofSi and diffusion of Si in SiGe indicate that temperature does have an influence on the compositionof the pile-up layer, though the range of achievable compositions is limited. The flux of Si due todiffusion of Si in SiGe relative to the oxidation-induced flux of Si out of the SiGe is integral to theformation and dimensions of a pile-up region. Two predictive relations were derived for describingthe dynamics of oxidation of SiGe. The first relation is given for determining the pile-up layerthickness as a function of oxide thickness and the composition of the pile-up layer. The secondrelation assumes a limited supply of Si and is for determination of the minimum initial thickness ofa SiGe layer to avoid oxidation of Ge. The validity of these equations was confirmedexperimentally by RBS and XPS data from the present work. The proposed models may be used innanostructuring of thin films of SiGe by oxidation and in the design of core-shell structures andtransistors. This is all done with a focus on oxidation of epitaxial thin films (< 100nm) ofSi

14 citations

Journal ArticleDOI
TL;DR: In this paper, the authors examined the kinetics of dry thermal oxidation of (111), (110), and (100) silicon-germanium (SiGe) thin epitaxial films and the redistribution of Ge near the oxidation interface with the aim of facilitating construction of single and multi-layered nano-structures.
Abstract: The present study examines the kinetics of dry thermal oxidation of (111), (110), and (100) silicon-germanium (SiGe) thin epitaxial films and the redistribution of Ge near the oxidation interface with the aim of facilitating construction of single and multi-layered nano-structures. By employing a series of multiple and single step oxidations, it is shown that the paramount parameter controlling the Ge content at the oxidation interface is the oxidation temperature. The oxidation temperature may be set such that the Ge content at the oxidation interface is increased, kept static, or decreased. The Ge content at the oxidation interface is modeled by considering the balance between Si diffusion in SiGe and the flux of Si into the oxide by formation of SiO2. The diffusivity of Si in SiGe under oxidation is determined for the three principal crystal orientations by combining the proposed empirical model with data from X-ray diffraction and variable angle spectroscopic ellipsometry. The orientation dependence o...

12 citations

Proceedings ArticleDOI
25 Apr 2004
TL;DR: This work attempts to improve the common understanding of multiple temperature testing by presenting previously unpublished data as well as deriving a simple model for bounding an IC's performance within the three dimensional space defined by VDD, frequency, and temperature.
Abstract: This work attempts to improve the common understanding of multiple temperature testing by presenting previously unpublished data as well as deriving a simple model for bounding an IC's performance within the three dimensional space defined by VDD, frequency, and temperature. The model is used to design new temperature screens to improve the resolution between healthy and defective ICs. Temperature based test data is presented for Scan, LBIST, and TDF based MinVDD measurements as well as transistor characteristics needed to parameterize the model. The test vehicles used are 0.25 /spl mu/m and 0.18 /spl mu/m CMOS ASICs fabricated by LSI logic.

12 citations


Cited by
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Journal ArticleDOI
Ali Dasdan1, Ivan Hom1
TL;DR: The consequences of ITD in STA are analyzed and a proper handling of ITd is proposed in an industrial sign-off STA tool, believed to be the first such work.
Abstract: In digital circuit design, it is typically assumed that cell delay increases with decreasing voltage and increasing temperature. This assumption is the basis of the cornering approach with cell libraries in static timing analysis (STA). However, this assumption breaks down at low supply voltages because cell delay can decrease with increasing temperature. This phenomenon is caused by a competition between mobility and threshold voltage to dominate cell delay. We refer to this phenomenon as the inverted temperature dependence (ITD). Due to ITD, it becomes very difficult to analytically determine the temperatures that maximize or minimize the delay of a cell or a path. As such, ITD has profound consequences for STA: (1) ITD essentially invalidates the approach of defining corners by independently varying voltage and temperature; (2) ITD makes it more difficult to find short paths, leading to difficulties in detecting hold time violations; and (3) the effect of ITD will worsen as supply voltages decrease and threshold voltage variations increase. This article analyzes the consequences of ITD in STA and proposes a proper handling of ITD in an industrial sign-off STA tool. To the best of our knowledge, this article is the first such work.

60 citations

Journal ArticleDOI
TL;DR: In this article, the authors studied the mechanism of formation of GRLs and determined the major driving forces of the enrichment process, and highlighted the particular role played by the Si 0.5Ge0.5 which is stabilized for various experimental conditions and strain levels.
Abstract: The fabrication of an ultrathin Ge-rich SiGe body on silicon on insulator (SOI) is highly challenging for the next generation of fully depleted complementary metal-oxide semiconductor devices that will be implemented in the near future. Ge-rich layers (GRLs) could be fabricated using a Ge enrichment process which takes place during dry thermal oxidation of SiGe thin films. While several studies make use of the GRL for many applications, the basic mechanism at work during the enrichment process is still unclear. In this study, we address the mechanism of formation of GRL and we determine the major driving forces of the enrichment process. We highlight the particular role played by the Si0.5Ge0.5 which is stabilized for various experimental conditions and strain levels. A systematic study demonstrates that the 50% Ge content is stabilized by a self-limited interdiffusion process regulated by the entropic term of the formation energy, which is a minimum at Si0.5Ge0.5 at the expense of the elasticity-driven i...

36 citations

Journal ArticleDOI
TL;DR: Al-induced crystallization of amorphous SixGe1−x (a-SixGe1 −x) solid solutions, with compositions over the entire range of the isomorphous Si-Ge system, was investigated in detail, at low temperatures from 150 to 400 ° C, by in situ X-ray diffraction while gradually increasing the annealing temperature until crystallization was completed.

25 citations

Journal ArticleDOI
TL;DR: In this article, the authors describe the enhancement of Ge concentration in sub-100-nm thin films of SiGe by dry thermal oxidation and present a model for determination of the Ge content in the pile-up layer along with appropriate values for the activation energy and preexponential constant for diffusion of Si in Si1-XGeX.
Abstract: The data and analysis presented herein aims to facilitate the design and manufacture of SiGe based nanostructures and devices by describing the enhancement of Ge concentration in sub-100-nm thin films of SiGe by dry thermal oxidation. Thin films of SiGe were restructured by using thermal oxidation induced self-organization of Si and Ge atoms to create a layer of enhanced Ge concentration. The dry thermal oxidations were carried out at temperatures between 800 °C and 1000 °C. The influence of temperature on the Ge content at the oxidation front, as measured by x-ray diffraction, is examined and supported by simulation results. A model for determination of the Ge content in the pile-up layer is presented along with appropriate values for the activation energy and pre-exponential constant for diffusion of Si in Si1-XGeX. This model may also be used for determination of the diffusivity of Si in Si1-XGeX by fitting the model results to the measured Ge concentration in the pile-up layer. It is observed that the...

15 citations

Proceedings ArticleDOI
20 Nov 2011
TL;DR: In this paper, a list schedule based test scheduling algorithm is proposed to find the earliest starting time of each test and each test is associated with a lower temperature bound and an upper temperature bound to define the temperature range within which the test must be applied.
Abstract: Recent research has shown that some defects are detect resilient under normal or high temperature, therefore tests for those defects must be applied under lower temperature. On the other hand, some tests need to be applied under high temperature to improve the detection sensitivity. Thus temperature dependent testing which applies tests at different temperature ranges is needed. This paper discusses and gives a formulation of the temperature dependent test scheduling problem. In the proposed test scheduling scheme, each test is associated with a lower temperature bound and an upper temperature bound to define the temperature range within which the test must be applied. A list schedule based test scheduling algorithm is proposed to find the earliest starting time of each test. Cooling period is inserted when the core temperature is too high and heating sequence is applied when the core temperature is below the required specified temperature for the core. Simulation studies are performed for ITC'02 SoC benchmarks and test scheduling results are shown.

12 citations