Eugene A. Fitzgerald

Bio: Eugene A. Fitzgerald is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Dislocation & Germanium. The author has an hindex of 37, co-authored 118 publications receiving 4258 citations. Previous affiliations of Eugene A. Fitzgerald include Singapore–MIT alliance & National University of Singapore.

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

Abstract: We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates

Abstract: We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si/sub 0.75/Ge/sub 0.26/ and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si/sub 1-x/Ge/sub x/ layer.

Dislocation dynamics in relaxed graded composition semiconductors

Abstract: Lattice-mismatched relaxed graded composition layers in the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems have recently been created with unprecedented high quality due to advances in understanding the impact of epitaxial growth conditions. The key process–property correlation is the impact of growth conditions on dislocation dynamics. In particular, the SiGe/Si system has recently been well explored experimentally, allowing the dislocation dynamic model to be tested. We show that the dislocation dynamics model is in general applicable to graded layers in any material system as long as dislocation flow is not impeded. In the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems, with moderately dislocated graded layers, these mechanisms can be absent under appropriate growth conditions. However, in all systems, threading dislocation impediments eventually occur under continued deformation through continued grading. The mechanism in SiGe/Si is related to the impediment of dislocation flow from the surface morphology and strain-fields from misfit dislocations. In the III–V systems, we observe that a planar defect, referred to here as branch defects, can form under a wide range of growth conditions, and these defects will lead to inhibited dislocation flow. The quantitative nature of these effects can be empirically modeled with the same dislocation dynamic model by incorporating a composition-dependent change in the effective strain experienced by threading dislocations during grading-induced deformation.

High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers

Abstract: The integration of Ge photodetectors on silicon substrates is advantageous for various Si-based optoelectronics applications. We have fabricated integrated Ge photodiodes on a graded optimized relaxed SiGe buffer on Si. The dark current in the Ge mesa diodes, Js=0.15 mA/cm2, is close to the theoretical reverse saturation current and is a record low for Ge diodes integrated on Si substrates. Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes exhibit an external quantum efficiency of η=12.6% at λ=1.3 μm laser excitation in the photodiodes. The improvement in Ge materials quality and photodiode performance is derived from an optimized relaxed buffer process that includes a chemical mechanical polishing step within the dislocated epitaxial structure.

Hole mobility enhancements in strained Si/Si1-yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1-xGex (x<y) virtual substrates

Abstract: We have achieved peak hole mobility enhancement factors of 5.15 over bulk Si in metal-oxide-semiconductor field-effect transistors (MOSFETs) by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. To further investigate hole transport in these dual channel structures, we study the effects of strain, alloy scattering, and layer thickness on hole mobility enhancements in MOSFETs based upon these layers. We show that significant performance boosts can be obtained despite the effects of alloy scattering and that the best hole mobility enhancements are obtained for structures with thin Si surface layers.

Spintronics: Fundamentals and applications

Abstract: Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

Abstract: 1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Abstract: Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Device scaling limits of Si MOSFETs and their application dependencies

Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

High-performance Ge-on-Si photodetectors

Abstract: The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.