Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Atomic layer deposition: an overview.

Atomic layer deposition(ALD), a chemical vapor deposition technique based on sequential self-terminating gas–solid reactions, has for about four decades been applied for manufacturing conformal inorganic material layers with thickness down to the nanometer range. Despite the numerous successful applications of material growth by ALD, many physicochemical processes that control ALD growth are not yet sufficiently understood. To increase understanding of ALD processes, overviews are needed not only of the existing ALD processes and their applications, but also of the knowledge of the surface chemistry of specific ALD processes. This work aims to start the overviews on specific ALD processes by reviewing the experimental information available on the surface chemistry of the trimethylaluminum/water process. This process is generally known as a rather ideal ALD process, and plenty of information is available on its surface chemistry. This in-depth summary of the surface chemistry of one representative ALD process aims also to provide a view on the current status of understanding the surface chemistry of ALD, in general. The review starts by describing the basic characteristics of ALD, discussing the history of ALD—including the question who made the first ALD experiments—and giving an overview of the two-reactant ALD processes investigated to date. Second, the basic concepts related to the surface chemistry of ALD are described from a generic viewpoint applicable to all ALD processes based on compound reactants. This description includes physicochemical requirements for self-terminating reactions,reaction kinetics, typical chemisorption mechanisms, factors causing saturation, reasons for growth of less than a monolayer per cycle, effect of the temperature and number of cycles on the growth per cycle (GPC), and the growth mode. A comparison is made of three models available for estimating the sterically allowed value of GPC in ALD. Third, the experimental information on the surface chemistry in the trimethylaluminum/water ALD process are reviewed using the concepts developed in the second part of this review. The results are reviewed critically, with an aim to combine the information obtained in different types of investigations, such as growth experiments on flat substrates and reaction chemistry investigation on high-surface-area materials. Although the surface chemistry of the trimethylaluminum/water ALD process is rather well understood, systematic investigations of the reaction kinetics and the growth mode on different substrates are still missing. The last part of the review is devoted to discussing issues which may hamper surface chemistry investigations of ALD, such as problematic historical assumptions, nonstandard terminology, and the effect of experimental conditions on the surface chemistry of ALD. I hope that this review can help the newcomer get acquainted with the exciting and challenging field of surface chemistry of ALD and can serve as a useful guide for the specialist towards the fifth decade of ALD research.

Surface chemistry of atomic layer deposition: A case study for the trimethylaluminum/water process

Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.

Band offsets of wide-band-gap oxides and implications for future electronic devices

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

We have examined the structure of ultrathin ZrO2 layers on Si(001) using medium energy ion scattering and cross-sectional transmission electron microscopy. Films can be deposited on SiO2 layers with highly abrupt interfaces by atomic layer deposition. On HF stripped Si(001), nucleation was inhibited, resulting in poorer film morphology. ZrO2 showed remarkable stability against silicate formation, with no intermixing even after high temperature oxidation. The oxide is vulnerable to high temperature vacuum annealing, with silicidation occurring at temperatures above 900 °C.

Structure and stability of ultrathin zirconium oxide layers on Si(001)

A combination of two complementary depth profiling techniques with sub-nm depth resolution, nuclear resonance profiling and medium energy ion scattering, and cross-sectional high-resolution transmission electron microscopy were used to study compositional and microstructural aspects of ultrathin (sub-10 nm) Al2O3 films on silicon. All three techniques demonstrate uniform continuous films of stoichiometric Al2O3 with abrupt interfaces. These film properties lead to the ability of making metal-oxide semiconductor devices with Al2O3 gate dielectric with equivalent electrical thickness in the sub-2 nm range.

High-resolution depth profiling in ultrathin Al2O3 films on Si

Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues

An experimental and modeling study of charge trapping related threshold voltage shifts in Al2O3 and HfO2 n-type field effect transistors (nFET) is reported. The dependence of threshold voltage, subthreshold slope, and gate leakage currents on stressing time and injected charge carrier density are investigated as a function positive bias stress voltage and temperature. Based on experimental data, a model for trapping of charges in the existing traps is developed. The model is similar to SiO2 charge trapping models with one exception. Unlike SiO2 models, the model assumes a continuous distribution in trapping capture cross sections. The model predicts that threshold voltage would increase with a power law dependence on stressing time and injected charge carrier density (Ninj) in the initial stages of stressing. The model calculates threshold voltage shifts as a function of stress time and Ninj, thereby provides estimates of threshold voltage shifts after 10 years lifetime. It also provides insights into the...

Evgeni Gusev

Papers

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Structure and stability of ultrathin zirconium oxide layers on Si(001)

High-resolution depth profiling in ultrathin Al2O3 films on Si

Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues

Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks