Analogue IC Design: the Current Mode Approach

A first proof-of-concept mm-sized implantable device using ultrasonic power transfer and a hybrid bi-directional data communication link is presented. Ultrasonic power transfer enables miniaturization of the implant and operation deep inside the body, while still achieving safe and high power levels (100 $\mu$ W to a few mWs) required for most implant applications. The current implant prototype measures 4 mm $\times $ 7.8 mm and is comprised of a piezoelectric receiver, an IC designed in 65 nm CMOS process and an off-chip antenna. The IC can support a maximum DC load of 100 $\mu$ W for an incident acoustic intensity that is $\sim $ 5% of the FDA diagnostic limit. This demonstrates the feasibility of providing further higher available DC power, potentially opening up new implant applications. The proposed hybrid bi-directional data link consists of ultrasonic downlink and RF uplink. Falling edge of the ultrasound input is detected as downlink data. The implant transmits an ultra-wideband (UWB) pulse sequence as uplink data, demonstrating capability of implementing an energy-efficient M-ary PPM transmitter in the future.

A mm-Sized Implantable Medical Device (IMD) With Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

In this paper, a universal charge-controlled mem-elements (including memristor, memcapacitor, and meminductor) emulator consisting of off-the-shelf devices is proposed. With the unchanged topology of the circuit, the emulator can realize memristor, memcapacitor, and meminductor, respectively. The proposed emulation circuit has a simple mathematical relationship and is constructed with few active devices and passive components, which not only reduces the cost but also facilitates reproduction and facilitates future application research. The grounding and floating forms of the circuit are demonstrated, and Multisim circuit simulation and breadboard experiments validate the emulator's effectiveness. Furthermore, a universal mem-elements chaotic circuit is designed by using the proposed mem-elements emulator and other circuit elements, which is a deformation circuit of Chua's dual circuit. In this circuit, no matter whether the mem-element is memristor, memcapacitor, or meminductor, the chaotic circuit structure does not change, and all can generate hyper-chaos.

A universal emulator for memristor, memcapacitor, and meminductor and its chaotic circuit.

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reli- ability, prevents overheating of the circuits and in particu- lar prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk- driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an exam- ple of application three operational transconductance amplifiers (OTA) based on these non-conventional tech- niques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 μW. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to verify the design functionality and corre- spondence with theory.

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

In this paper, novel non-conventional techniques, 1 named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4 V with a rail-to-rail voltage swing capability and total power consumption of mere 10 μW. PSpice simulation results using the 0.18 μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

Memristor emulator based on TiO 2 model is introduced. The proposed circuit uses current mode building block DVCCTA (Differential Voltage Current Conveyor Transconductance Amplifier) using 0.25 µm CMOS technology. The presented circuit uses single CMOS based DVCCTA, three resistors and one capacitor. It can operate up to 1 MHz in both the incremental and decremental configuration by interchanging the connections. Theoretical analysis of the proposed circuit resulting in the equivalent memristance equation is done and non-ideal analysis is also included. PSPICE simulations are performed. Simulation results agree well with theoretical assumption. To verify the practicability of the circuit, PCB prototype has been made using AD844AN and CA3080. The experimental demonstration is carried out for 50 kHz and 100 kHz. Moreover, the circuit has also been tested for non-volatility features. It is observed from the experimental test result and using 0.25 µm CMOS technology that maximum frequency is 10 kHz and 50 kHz respectively. To check the functionality of the circuit two combinations of memristor are connected in serial and parallel and desired results are obtained. Memristor based high pass filter is also discussed so as to study the memristor behavior in comparison to the resistor.

Fabian Khateb

Papers

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

Single DVCCTA based high frequency incremental/decremental memristor emulator and its application

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Fractional-order filters based on low-voltage DDCCs