Fabien Rozé

Bio: Fabien Rozé is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Thermal oxidation & Oxide. The author has an hindex of 3, co-authored 5 publications receiving 12 citations. Previous affiliations of Fabien Rozé include European Automobile Manufacturers Association.

Oxidation kinetics of Si and SiGe by dry rapid thermal oxidation, in-situ steam generation oxidation and dry furnace oxidation

Abstract: The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to today's technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 A to 150 A range grown with oxidation temperatures between 850 and 1100 °C were targeted. The present work shows first that for all investigated processes, oxidation follows a parabolic regime even for thin oxides, which indicates a diffusion-limited oxidation regime. We also observe that, for all investigated processes, the SiGe oxidation rate is systematically higher than that of Si. The amplitude of the variation of oxidation kinetics of SiGe with respect to Si is found to be strongly dependent on the process type. Second, a new quantitative analysis methodology of oxidation kinetics is introduced. This methodology allows us to highlight the dependence of oxidation kinetics on the Ge concentration at the oxidation interface, which is modulated by the pile-up mechanism. Our results show that the oxidation rate increases with the Ge concentration at the oxidation interface.

Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects

Abstract: Recent progress in materials, processes and integration schemes to reduce line resistance (Line-R) of damascene Cu and alternative conductors (damascene Co and subtractive Ru) are reviewed, including (1) graphene/Co capped Cu to achieve both EM reliability and Line-R reduction (2) nanosecond laser anneal of Ru blanket films for subtractive-etched interconnects, (3) single damascene Cu, which is potentially one way to extend Cu to extreme nodes, and (4) Co/Cu composite integration to preserve Cu power rails. Finally, the technology shift from Cu to alternative conductors is discussed from the viewpoint of Line-R crossover.

SiGe oxidation kinetics and oxide density measured by resonant soft X-ray reflectivity

Abstract: Ultrathin compressively strained SiGe layers is one of the most promising materials for high mobility channels of p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFETs). Fabrication of such layers as well as formation of high-quality gate oxides on SiGe both involve SiGe thermal oxidation processes. These processes require well-controlled oxidation kinetics and oxide properties. This work discusses oxidation kinetics of SiGe in light of the characterization of the thermal oxide density by the Resonant Soft X-Ray Reflectivity (R-SoXR) technique.

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Abstract: The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

High performance 4.5-nm-thick compressively-strained Ge-on-insulator pMOSFETs fabricated by Ge condensation with optimized temperature control

Abstract: We report high performance extremely-thin-body (ETB) Ge-on-Insulator (GOI) pMOSFETs fabricated by a new Ge condensation process with minimized temperature cycles and slow cooling-down rate. This new condensation process effectively suppresses strain relaxation during Ge condensation and creates high compressive strain. By combining the highly-strained GOI substrates with a digital etching process, we successfully realized 4.5-nm-thick strained-GOI pMOSFETs with excellent GOI thickness uniformity. The MOSFETs exhibit highest hole mobility of 138 cm2/Vs in GOI thickness less than 5 nm and the hole mobility enhancement of 2.0 over that of best performance GOI pMOSFETs in this thickness range.

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm.

Abstract: Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

Etch Control and SiGe Surface Composition Modulation by Low Temperature Plasma Process for Si/SiGe Dual Channel Fin Application

Abstract: In this study, we discuss Si-SiGe etch characteristics as well as SiGe surface composition modification. It is required to etch Si and SiGe simultaneously for Si/SiGe dual channel Fin-FETs. Therefore, etch control of these two materials is desired. However, not only halogen chemistries but also physical sputtering etch SiGe selective to Si. We found that Si can be etched faster than SiGe by hydrogen plasma. Our analysis presents that hydrogen bonds selectively with Si rather than Ge, which leads to Si selective removal. As for SiGe surface modification, realizing Si-rich surface in SiGe is known to improve SiGe/high-k interface quality in advanced CMOS. It is also presented that the low-temperature hydrogen plasma induces Si-surface segregation (i.e., Si-rich surface) in SiGe, which is confined near the top-surface region. We proposed this may be caused by ion-energy-driven surface reaction. Our study also shows that Ge/Si ratio increases with plasma exposure time, which has correlation with surface roughness. Using the hydrogen plasma and conventional halogen plasma, we successfully demonstrate to etch Si/SiGe dual channel fins with depth and CD value control.

The Diffusion Mechanism of Ge During Oxidation of Si/SiGe Nanofins.

Abstract: A recently discovered, enhanced Ge diffusion mechanism along the oxidizing interface of Si/SiGe nanostructures has enabled the formation of single-crystal Si nanowires and quantum dots embedded in a defect-free, single-crystal SiGe matrix. Here, we report oxidation studies of Si/SiGe nanofins aimed at gaining a better understanding of this novel diffusion mechanism. A superlattice of alternating Si/Si0.7Ge0.3 layers was grown and patterned into fins. After oxidation of the fins, the rate of Ge diffusion down the Si/SiO2 interface was measured through the analysis of HAADF-STEM images. The activation energy for the diffusion of Ge down the sidewall was found to be 1.1 eV, which is less than one-quarter of the activation energy previously reported for Ge diffusion in bulk Si. Through a combination of experiments and DFT calculations, we propose that the redistribution of Ge occurs by diffusion along the Si/SiO2 interface followed by a reintroduction into substitutional positions in the crystalline Si.

Study of Thermal Oxidation of SiGe for Advanced CMOS FD-SOI Technologies

Abstract: La reduction continue des dimensions des transistors depuis les annees 60 est a l’origine de l’explosion des usages de l’electronique. Toutefois, la reduction des dimensions a l’echelle nanometrique s’accompagne de nouvelles difficultes qui tendent a limiter les gains des transistors en termes de performances et de consommation.Afin de surmonter ces obstacles et maintenir cette dynamique, des canaux a base de nouveaux materiaux a forte mobilite et de nouvelles architectures de transistors sont desormais utilisees ou a l’etude. L’interet de films SiGe contraint en compression sur isolant (SGOI: SiGe-On-Insulator) ultra-minces est double : ils beneficient de la forte mobilite des trous du SiGe contraint en compression ainsi que du meilleur controle electrostatique des structures dites « sur isolant ». Des films SGOI presentant une forte concentration en Ge et une importante contrainte peuvent etre fabriques par une technique industrielle appelee condensation. Cette technique repose sur deux processus simultanes : l’oxydation thermique et selective du SiGe (seul le Si est oxyde) et l’inter-diffusion du SiGe entre l’oxyde thermique et l’oxyde enterre qui se comporte comme une barriere a la diffusion.L’utilisation de cette technique dans un environnement industriel necessite de relever deux defis : maitriser les mecanismes et la cinetique d’oxydation, et atteindre les plus fortes contraintes et qualites cristallines pour lesfilms SGOI.La cinetique de plusieurs procedes d’oxydation industriels et pertinents au regard des besoins technologiques actuels est etudiee a l’aide d’une nouvelle methodologie d’analyse quantitative. Nous etablissons une correlationentre le coefficient de diffusion de l’espece oxydante, qui determine la cinetique d’oxydation, la concentration en Ge a l’interface d’oxydation, et la densite de l’oxyde mesuree par reflectivite de rayons X sur une ligne desynchrotron.Puis, nous avons fabrique des films SGOI presentant des concentrations en Ge jusqu’a 80%. Nous discutons l’evolution de la contrainte de ces films en fonction des parametres du procede et des niveaux de contrainte. Enfin,nous mettons en evidence les effets du procede de condensation sur la qualite cristalline du film SiGe aux interfaces avec les oxydes grâce a l’effet de canalisation d’une technique de retrodiffusion d’ions a moyenne energie (MEIS : Medium Energy Ion Scattering)