scispace - formally typeset
Search or ask a question
Author

Fabrice Labtau

Bio: Fabrice Labtau is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: Error detection and correction & Binary erasure channel. The author has an hindex of 1, co-authored 1 publications receiving 6 citations.

Papers
More filters
Proceedings ArticleDOI
08 Sep 1998
TL;DR: An approximation of the bit error rate of the cascade of a linear block code and a memoryless binary channel is proposed, which can be considered as a single binary symmetric channel, with known transition probability, and can be used as such for further processing.
Abstract: In many joint source-channel coding applications, there is a need to assess the performance of a system on a given channel, with different combinations of channel codes What is interesting is to know some measure of the overall bit error rate, in order to design the source and/or channel codes accordingly We propose here an approximation of the bit error rate of the cascade of a linear block code and a memoryless binary channel With this approximation, both of these components can be considered in this respect as a single binary symmetric channel, with known transition probability, and can be used as such for further processing We also show some possible applications in joint source-channel coding schemes

6 citations


Cited by
More filters
01 Dec 1978
TL;DR: In this paper, a combined source-channel coding approach is described for the encoding, transmission and remote reconstruction of image data, where the source encoder employs two-dimensional (2-D) differential pulse code modulation (DPCM).
Abstract: A combined source-channel coding approach is described for the encoding, transmission and remote reconstruction of image data. The source encoder employs two-dimensional (2-D) differential pulse code modulation (DPCM). This is a relatively efficient encoding scheme in the absence of channel errors. In the presence of channel errors, however, the performance degrades rapidly. By providing error control protection to those encoded bits which contribute most significantly to image reconstruction, it is possible to minimize this degradation without sacrificing transmission bandwidth. The result is a relatively robust design which is reasonably insensitive to channel errors and yet provides performance approaching the rate-distortion bound. Analytical results are provided for assumed 2-D autoregressive image models while simulation results are described for real-world images.

167 citations

Journal ArticleDOI
TL;DR: The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix, and shows that the SCU is able to recover from transient faults.
Abstract: This paper describes a novel architecture of fault tolerant solid state mass memory (SSMM) for satellite applications. Mass memories with low-latency time, high throughput, and storage capabilities cannot be easily implemented using space qualified components, due to the inevitable technological delay of these kind of components. For this reason, the choice of commercial off the shelf (COTS) components is mandatory for this application. Therefore, the design of an electronic system for space applications, based on commercial components, must match the reliability requirements using system level methodologies. In the proposed architecture, error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller is developed by applying fault tolerant design solutions. The main features of the SSMM are the dynamic reconfiguration capability, and the high performances which can be gracefully reduced in case of permanent faults, maintaining part of the system functionality. The paper shows the system design methodology, the architecture, and the simulation results of the SSMM. The properties of the building blocks are described in detail both in their functionality and fault tolerant capabilities. A detailed analysis of the system reliability and data integrity is reported. The graceful degradation capability of our system allows different levels of acceptable performances, in terms of active I/O link interfaces and storage capability. The results also show that the overall reliability of the SSMM is almost the same using different RS coding schemes, allowing a dynamic reconfiguration of the coding to reduce the latency (shorter codewords), or to improve the data integrity (longer codewords). The use of a scrubbing technique can be useful if a high SEU rate is expected, or if the data must be stored for a long period in the SSMM. The reported simulations show the behavior of the SSMM in presence of permanent and transient faults. In fact, we show that the SCU is able to recover from transient faults. On the other hand, using a spare microcontroller also hard faults can be tolerated. The distributed file system confines the unrecoverable fault effects only in a single I/O Interface. In this way, the SSMM maintains its capability to store and read data. The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix.

66 citations

Journal ArticleDOI
TL;DR: In this paper, an innovative fault tolerant solid state mass memory (FTSSMM) architecture is described, which is based on commercial off-the-shelf (COTS) components.
Abstract: In this paper, an innovative fault tolerant solid state mass memory (FTSSMM) architecture is described. Solid state mass memories (SSMMs) are particularly suitable for space applications and more in general for harsh environments such us, for example, nuclear accelerators or avionics. The presented FTSSMM design has been entirely based on commercial off the shelf (COTS) components. In fact, cost competitive and very high performance SSMMs cannot be easily implemented by using space qualified components, due the technological gap and very high cost characterizing these components. In order to match the severe reliability requirements of space applications a COTS-based apparatus must be designed by using suitable system level methodologies (Kluth, 1996 and Fichna, 1998). In the proposed architecture, error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller has been designed by applying suitable fault tolerant design techniques. Different from other proposed solutions, our architecture fully exploits the reconfiguration capabilities of Reed-Solomon (RS) codes, discriminates between permanent and transient faults reducing the use of spare elements, and provides dynamic reconfiguration and graceful degradation capability, i.e., the FTSSMM performances are gracefully reduced in case of permanent faults, maintaining part of the system functionality. The paper shows the FTSSMM design methodology, the architecture, the reliability analysis, some simulation results, and a description of its implementation based on fast prototyping techniques.

48 citations

Proceedings ArticleDOI
07 Oct 2001
TL;DR: Two new algorithms have been developed, based on more accurate modeling for luminance masking and on experimental tests for texture masking, for the benefit of a best performing fingerprinting scheme inside wavelet decompressors.
Abstract: This paper proposes some modifications to reference models of the human visual system for the benefit of a best performing fingerprinting scheme inside wavelet decompressors. Two new algorithms have been developed, based on more accurate modeling for luminance masking and on experimental tests for texture masking. In order to manifest the improvements, the insertion gain of the masks relative to non-perceptual watermarking schemes is calculated and compared to the one obtained by the reference technique. Also, the masks' energy distribution is checked to validate them as weighting functions of the watermark.

26 citations

Proceedings ArticleDOI
08 Nov 2004
TL;DR: This paper introduces a very flexible approach for the evaluation of bit error rates (BER) attainable on storage systems which use Reed Solomon codes based on the use of a Markov model to evaluate the probabilities of having an uncorrectable codeword.
Abstract: This paper introduces a very flexible approach for the evaluation of bit error rates (BER) attainable on storage systems which use Reed Solomon codes. These evaluations are based on the use of a Markov model to evaluate the probabilities of having an uncorrectable codeword. Differently from previous literature, the reported approach can take into account the impact of both erasures and random errors, allowing a smaller degree of approximation and better evaluation of BER improvement related to the introduction of scrubbing techniques. The flexibility of the proposed method is finally shown by applying it to different cases of interest.

22 citations