The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. However, the tradeoff between current efficiency and transient response speed has limited its applications. In this brief, a coarse–fine-tuning technique with burst-mode operation is proposed to the D-LDO. Once the voltage undershoot/overshoot is detected, the coarse tuning quickly finds out the coarse control word in which the load current should be located, with large power MOS strength and high sampling frequency for a fixed time. Then, the fine-tuning, with reduced power MOS strength and sampling frequency, regulates the D-LDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. The proposed D-LDO is verified in a 65-nm CMOS process with a 0.01-mm2 active area. The measured voltage undershoot and overshoot are 55 and 47 mV, respectively, with load steps of 2 to 100 mA with a 20-ns edge time. The quiescent current is 82 $\mu\textrm{A}$ , with a 0.43-ps figure of merit achieved. Moreover, the reference tracking speed is 1.5 $\textrm{V}/\mu\textrm{s}$ .

A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

Since the seventies, positron emission tomography (PET) has become an invaluable medical molecular imaging modality with an unprecedented sensitivity at the picomolar level, especially for cancer diagnosis and the monitoring of its response to therapy. More recently, its combination with x-ray computed tomography (CT) or magnetic resonance (MR) has added high precision anatomic information in fused PET/CT and PET/MR images, thus compensating for the modest intrinsic spatial resolution of PET. Nevertheless, a number of medical challenges call for further improvements in PET sensitivity. These concern in particular new treatment opportunities in the context personalized (also called precision) medicine, such as the need to dynamically track a small number of cells in cancer immunotherapy or stem cells for tissue repair procedures. A better signal-to-noise ratio (SNR) in the image would allow detecting smaller size tumours together with a better staging of the patients, thus increasing the chances of putting cancer in complete remission. Moreover, there is an increasing demand for reducing the radioactive doses injected to the patients without impairing image quality. There are three ways to improve PET scanner sensitivity: improving detector efficiency, increasing geometrical acceptance of the imaging device and pushing the timing performance of the detectors. Currently, some pre-localization of the electron-positron annihilation along a line-of-response (LOR) given by the detection of a pair of annihilation photons is provided by the detection of the time difference between the two photons, also known as the time-of-flight (TOF) difference of the photons, whose accuracy is given by the coincidence time resolution (CTR). A CTR of about 10 picoseconds FWHM will ultimately allow to obtain a direct 3D volume representation of the activity distribution of a positron emitting radiopharmaceutical, at the millimetre level, thus introducing a quantum leap in PET imaging and quantification and fostering more frequent use of 11C radiopharmaceuticals. The present roadmap article toward the advent of 10 ps TOF-PET addresses the status and current/future challenges along the development of TOF-PET with the objective to reach this mythic 10 ps frontier that will open the door to real-time volume imaging virtually without tomographic inversion. The medical impact and prospects to achieve this technological revolution from the detection and image reconstruction point-of-views, together with a few perspectives beyond the TOF-PET application are discussed.

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Roadmap toward the 10 ps time-of-flight PET challenge

Digitally implementable LDOs embedded within digital functional units augment their analog counterparts for ultrafine-grained power management in digital ICs. Digital load circuits represent load currents with large and infrequent current transients and require a wide voltage range of operation, preferably down to the threshold voltage ( $V_{{\rm TH}}$ ) of the transistor. This paper presents a discrete-time, fully digital, scan-programmable LDO macro in a low-power 0.13-μm technology operating down to 1.07×, the transistor $V_{{\rm TH}}$ , and featuring greater than 90% current efficiency across a 50× current range through fine-grained clock gating and adaptive control. An 8× improvement in transient response time to large load steps is achieved through switched mode control. Both transient and steady-state operation models and measurements of the LDO are presented.

All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits

This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control. For responding to instant load transients, the proposed high-pass AA loop momentarily adjusts the unit current of the power switch array, and significantly reduces the voltage spikes. In the proposed D-LDO, the overall 512 output current steps are divided into three sub-sections controlled by coarse/fine loops with carry-in/out operations. Therefore, the required shift register (SR) length is reduced, and a 9-bit output current resolution is realized by using only 28-SR bits. Besides, the coarse-tuning loop helps to reduce the recovery time, while the fine-tuning loop improves the output accuracy. To eliminate the limit cycle oscillation and reduce the quiescent current, a freeze mode is added after the fine-tuning operation. To reduce the output glitches and the recovery time, a nonlinear coarse word control is designed for the carry-in/out operations. The D-LDO is fabricated in a 65-nm general purpose CMOS process. A maximum voltage undershoot/overshoot of 105 mV is measured with a 10-mA/1-ns load step and a total capacitor of only 100 pF. Thus, the resulting figure-of-merit is 0.23 ps.

An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator

This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $ dynamic load range.

A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control

This paper introduces a multi-step switching scheme for a digital low dropout regulator (DLDO) that emerges as a new way of achieving nanosecond-transient and fine-grained on-chip voltage regulation. The multi-step switching scheme takes advantage of the adaptive pipeline control and asynchronous clocking for area- and power-efficient digital controller utilization. It speeds up the transient response by varying the pass transistor sizing in two available lengths of coarse steps as per the perturbation, while maintaining a small output voltage ripple by toggling in a finer step at steady operation. A prototype proving the proposed concept, i.e., a 0.6–1.0-V input, 50–200-mV dropout, and 500-mA maximum loading DLDO with an on-chip 1.5-nF output capacitor, is fabricated in a 65-nm CMOS process to verify the effectiveness of this scheme. By employing the multi-step switching scheme and adaptive control, the DLDO achieved a fast transient response to nanoseconds loading current change, and a 100 mV per 10-ns reference voltage switching, as well as a resolution of 768 levels (~9.5 bits) with a 5-mV output ripple. The quiescent current consumed by this DLDO at steady operation is down to $300~{\mu }\text{A}$ .

A Nanosecond-Transient Fine-Grained Digital LDO With Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control

With the die area of modern processors growing larger and larger, the IR drop across the power supply rail due to its parasitic resistance becomes considerable. There is an urgent demand for local power regulation to reduce the IR drop and to enhance transient response. A distributed power-delivery grid (DPDG) is an attractive solution for large area power-supply applications. The dual-loop distributed micro-regulator in [1] achieves a tight regulation and fast response, but suffers from large ripple and high power consumption due to the comparator-based regulator. Digital low-dropout regulators (DLDOs) [2] can be used as local micro-regulators to implement a DPDG, due to their low-voltage operation and process scalability. Adaptive control [3], asynchronous 3D pipeline control [4], analog-assisted tri-loop control [5], and event-driven PI control [6] are proposed to enhance the transient response speed. However, digital LDOs suffer from the intrinsic limitations of large output ripple and narrow current range. This paper presents an on-chip DPDg with cooperative regulation based on an analog-assisted digital LDO (AADLDO), which inherits the merits of low output ripple and sub-LSB current supply ability from the analog control, and the advantage of low supply voltage operation and adaptive fast response from the digital control.

A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOS

Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific minimum supply voltages. Point-of-load low-dropout regulators (LDOs) are used to power these modules as per the required applications, from a global supply rail Vdd. The global Vdd is noisy and can be varied within a wide range, which adds to the difficulty of designing LDOs in such applications.

5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over −20dB PSR at 0.2V lowest supply voltage

A 65-nm external capacitor-less asynchronous digital low drop-out regulator (DLDO) with adaptive sizing and fast transient response is presented in this paper. Operating at a wide input voltage range from as low as 0.6V to 1V, this DLDO is capable of delivering a maximum current of 500mA with 50mV drop-out voltage. The proposed adaptive sizing featured by row-column-bit 3-dimensional (3D) power stage and its asynchronous adaptive digital pipeline control have enabled a fast transient response to nanoseconds' loading current change and a 200mV per 10ns reference voltage switching, as well as a fine resolution of 768 levels (~9.5 bits) with a 5mV output ripple. The quiescent current consumed by this DLDO at steady operation is as low as 300μA over the whole input range.

A 0.6–1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS

A digital low drop-out regulator (DLDO) load regulation enhancement technique which includes soft multi-step switching and adaptive timing is presented in this paper. As multi-step switching is widely used to balance the speed and resolution, a power-efficient method to improve the poor resolution during the switching between coarse- and finegrained regulations is in demand. The proposed technique, especially targeting at eliminating the undesired ripple voltage during multi-step switching, is implemented in a 65-nm asynchronous DLDO. This DLDO operates at an input voltage of 0.6V to 1V, and delivers a maximum of 500mA current with a 50mV drop-out voltage. In addition to responding to a nanoseconds' 500mA load current step and a 50mV per 10ns reference voltage change, an enhanced load regulation of 0.15mV/mA is achieved by adopting the proposed techniques.

Fan Yang

Papers

A Nanosecond-Transient Fine-Grained Digital LDO With Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control

A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOS

5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over −20dB PSR at 0.2V lowest supply voltage

A 0.6–1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS

Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS