F
Fanchieh Yee
Researcher at IBM
Publications - 7
Citations - 191
Fanchieh Yee is an academic researcher from IBM. The author has contributed to research in topics: Dataflow architecture & Floating point. The author has an hindex of 4, co-authored 7 publications receiving 101 citations.
Papers
More filters
Proceedings ArticleDOI
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference
Bruce M. Fleischer,Sunil Shukla,Matthew M. Ziegler,Joel Abraham Silberman,Jinwook Oh,Vijavalakshmi Srinivasan,Jungwook Choi,Silvia Melitta Mueller,Ankur Agrawal,Tina Babinsky,Nianzheng Cao,Chia-Yu Chen,Pierce Chuang,Thomas W. Fox,George D. Gristede,Michael A. Guillorn,Howard M. Haynie,Michael J. Klaiber,Dongsoo Lee,Shih-Hsien Lo,Gary W. Maier,Michael R. Scheuermann,Swagath Venkataramani,Christos Vezyrtzis,Naigang Wang,Fanchieh Yee,Ching Zhou,Pong-Fei Lu,Brian W. Curran,Lel Chang,Kailash Gopalakrishnan +30 more
TL;DR: A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers by employing a dataflow architecture and an on-chip scratchpad hierarchy.
Journal ArticleDOI
Efficient AI System Design With Cross-Layer Approximate Computing
Swagath Venkataramani,Xiao Sun,Naigang Wang,Chia-Yu Chen,Jungwook Choi,Mingu Kang,Ankur Agarwal,Jinwook Oh,Shubham Jain,Tina Babinsky,Nianzheng Cao,Thomas W. Fox,Bruce M. Fleischer,George D. Gristede,Michael A. Guillorn,Howard M. Haynie,Hiroshi Inoue,Kazuaki Ishizaki,Michael J. Klaiber,Shih-Hsien Lo,Gary W. Maier,Silvia Melitta Mueller,Michael R. Scheuermann,Eri Ogawa,Marcel Schaal,Mauricio J. Serrano,Joel Abraham Silberman,Christos Vezyrtzis,Wei Wang,Fanchieh Yee,Jintao Zhang,Matthew M. Ziegler,Ching Zhou,Moriyoshi Ohara,Pong-Fei Lu,Brian W. Curran,Sunil Shukla,Vijayalakshmi Srinivasan,Leland Chang,Kailash Gopalakrishnan +39 more
TL;DR: RaPiD, a multi-tera operations per second (TOPS) AI hardware accelerator core that is built from the ground-up using AxC techniques across the stack including algorithms, architecture, programmability, and hardware, is presented.
Journal ArticleDOI
A Scalable Multi-TeraOPS Core for AI Training and Inference
Sunil Shukla,Bruce M. Fleischer,Matthew M. Ziegler,Joel Abraham Silberman,Jinwook Oh,Vijayalakshmi Srinivasan,Jungwook Choi,Silvia Melitta Mueller,Ankur Agrawal,Tina Babinsky,Nianzheng Cao,Chia-Yu Chen,Pierce Chuang,Thomas W. Fox,George D. Gristede,Michael A. Guillorn,Howard M. Haynie,Michael J. Klaiber,Dongsoo Lee,Shih-Hsien Lo,Gary W. Maier,Michael R. Scheuermann,Swagath Venkataramani,Christos Vezyrtzis,Naigang Wang,Fanchieh Yee,Ching Zhou,Pong-Fei Lu,Brian W. Curran,Leland Chang,Kailash Gopalakrishnan +30 more
TL;DR: This letter presents a multi-TOPS AI accelerator core for deep learning training and inference that achieves >90% sustained utilization across the range of neural network topologies by employing a dataflow architecture to provide high throughput and an on-chip scratchpad hierarchy to meet the bandwidth demands of the compute units.
Proceedings ArticleDOI
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
Jinwook Oh,Sae Kyu Lee,Mingu Kang,Matthew M. Ziegler,Joel Abraham Silberman,Ankur Agrawal,Swagath Venkataramani,Bruce M. Fleischer,Michael A. Guillorn,Jungwook Choi,Wei Wang,Silvia Melitta Mueller,Shimon Ben-Yehuda,James J. Bonanno,Nianzheng Cao,Robert Casatuta,Chia-Yu Chen,Matthew Cohen,Erez Ophir,Thomas W. Fox,George D. Gristede,Howard M. Haynie,Vicktoria Ivanov,Siyu Koswatta,Shih-Hsien Lo,Martin Lutz,Gary W. Maier,Alex Mesh,Yevgeny Nustov,Scot H. Rider,Marcel Schaal,Michael R. Scheuermann,Xiao Sun,Naigang Wang,Fanchieh Yee,Ching Zhou,Vinay Velji Shah,Brian W. Curran,Vijayalakshmi Srinivasan,Pong-Fei Lu,Sunil Shukla,Kailash Gopalakrishnan,Leland Chang +42 more
TL;DR: A processor core is presented for AI training and inference products that achieves leading-edge compute efficiency for robust fp16 training via efficient heterogeneous 2-D systolic array-SIMD compute engines leveraging compact DLFloat16 FPUs.
Proceedings ArticleDOI
Row Based Dual-VDD Island Generation and Placement
TL;DR: This paper adopts the row-based dual-supply voltage (DSV) scheme, and presents a two-stage flow to generate voltage islands for every two mirrored circuit rows and place gates legally inside each island.