scispace - formally typeset
Search or ask a question
Author

Farid N. Najm

Other affiliations: Altera, University of Illinois at Urbana–Champaign, Xilinx  ...read more
Bio: Farid N. Najm is an academic researcher from University of Toronto. The author has contributed to research in topics: Grid & Very-large-scale integration. The author has an hindex of 43, co-authored 188 publications receiving 7530 citations. Previous affiliations of Farid N. Najm include Altera & University of Illinois at Urbana–Champaign.


Papers
More filters
Journal ArticleDOI
TL;DR: A review of the power estimation techniques that have recently been proposed for very large scale integrated (VLSI) circuits is presented.
Abstract: With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

696 citations

Journal ArticleDOI
Farid N. Najm1
TL;DR: It is shown how the density values at internal nodes can be used to study circuit reliability by estimating theaverage power and ground currents; the average power dissipation; the susceptibility to electromigration failures; and the extent of hot-electron degradation.
Abstract: Noting that a common element in most causes of runtime failure is the extent of circuit activity, i.e. the rate at which its nodes are switching, the author proposes a measure of activity, called the transition density, which may be defined as the average switching rate at a circuit node. An algorithm is also presented to propagate density values from the primary inputs to internal and output nodes. To illustrate the practical significance of this work, it is shown how the density values at internal nodes can be used to study circuit reliability by estimating the average power and ground currents; the average power dissipation; the susceptibility to electromigration failures; and the extent of hot-electron degradation. The density propagation algorithm has been implemented in a prototype density simulator which is used to assess the validity and feasibility of the approach experimentally. The results show that the approach is very efficient, and makes possible the analysis of VLSI circuits. >

430 citations

Journal ArticleDOI
TL;DR: A power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques, and the superiority of the approach is discussed.
Abstract: The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach. >

359 citations

Proceedings ArticleDOI
05 May 1997
TL;DR: The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated.
Abstract: In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing the power supply voltage. This requires that the transistor threshold voltages be reduced as well to maintain adequate performance and noise margins. However, this increases the subthreshold leakage current of p and n MOSFETs, which starts to offset the power savings obtained from power supply reduction. This problem will worsen in future generations of technology, as threshold voltages are reduced further. In order to overcome this, we propose a design technique that can be used during logic design in order to reduce the leakage current and power. We target designs where parts of the circuit are put in "standby" mode when not in use, which is becoming a common approach for low power design. The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated. We give an efficient algorithm for computing a good low leakage power state. We demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54% for some circuits.

298 citations

Journal ArticleDOI
TL;DR: Experimental results show that the proposed method is very efficient as well as suitable for both DC and transient analysis of power grids, and reduced to a coarser structure, and the solution is mapped back to the original grid.
Abstract: Modern submicron very large scale integration designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. The authors propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both de and transient analysis of power grids.

268 citations


Cited by
More filters
Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

Journal ArticleDOI
TL;DR: The other source of power dissipation in microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips.
Abstract: Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips. Until recently, only dynamic power has been a significant source of power consumption, and Moore's law helped control it. However, power consumption has now become a primary microprocessor design constraint; one that researchers in both industry and academia will struggle to overcome in the next few years. Microprocessor design has traditionally focused on dynamic power consumption as a limiting factor in system integration. As feature sizes shrink below 0.1 micron, static power is posing new low-power design challenges.

1,233 citations