F
Farzan Fallah
Researcher at Fujitsu
Publications - 76
Citations - 2244
Farzan Fallah is an academic researcher from Fujitsu. The author has contributed to research in topics: Leakage (electronics) & CMOS. The author has an hindex of 25, co-authored 75 publications receiving 2200 citations. Previous affiliations of Farzan Fallah include University of Southern California & Massachusetts Institute of Technology.
Papers
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Journal ArticleDOI
Leakage current reduction in CMOS VLSI circuits by input vector control
TL;DR: Two runtime mechanisms for reducing the leakage current of a CMOS circuit are described and a design technique for applying the minimum leakage input to a sequential circuit is presented, which shows that it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
Journal ArticleDOI
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
Farzan Fallah,Massoud Pedram +1 more
TL;DR: Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control.
Proceedings ArticleDOI
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
TL;DR: The contribution of this work is the development of a vector generation procedure targeting the observability-based statement coverage metric, and a novel technique to set up constraints based on the chosen coverage metric for vector generation.
Proceedings ArticleDOI
OCCOM: efficient computation of observability-based code coverage metrics for functional verification
TL;DR: This paper provides the details of an efficient method to compute an Observability-based Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs and offers a more accurate assessment of design verification coverage than line coverage.
Proceedings ArticleDOI
Functional vector generation for HDL models using linear programming and 3-satisfiability
TL;DR: This work presents a new HDL-satisfiability checking algorithm that works directly on the HDL model, and the primary feature of this algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of datapath modules, and 3-SAT checking for logic equations that governs the behaviorof control modules.