F
Fazal Hameed
Researcher at Dresden University of Technology
Publications - 33
Citations - 477
Fazal Hameed is an academic researcher from Dresden University of Technology. The author has contributed to research in topics: Cache & Static random-access memory. The author has an hindex of 12, co-authored 27 publications receiving 293 citations. Previous affiliations of Fazal Hameed include Institute of Space Technology & Karlsruhe Institute of Technology.
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Journal ArticleDOI
Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade
Robin Bläsing,Asif Ali Khan,Panagiotis Ch. Filippou,Chirag Garg,Fazal Hameed,Jeronimo Castrillon,Stuart S. P. Parkin +6 more
TL;DR: An overview of the major developments of RTM technology from both the physics and computer architecture perspectives over the past decade is provided, enabling a new era of cache, graphical processing units, and high capacity memory devices.
Journal ArticleDOI
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0
TL;DR: An integer linear programming (ILP) formulation for optimal data placement in RMs is presented, and existing offset assignment heuristics, originally proposed for random-access memories, are revisited.
Proceedings ArticleDOI
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
TL;DR: This paper's proposed set mapping policy reduces the average DRAM cache access latency compared to state-of-the-art DRAM set mapping policies that are optimized for either HL or MR by 29.3% and 12.1%, respectively.
Journal ArticleDOI
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache
TL;DR: A selective read policy is proposed for the STT-RAM which fetches unneeded cache lines into the RB that are likely to be reused and reduces the number of reads/writes and thereby decreases the energy consumption.
Journal ArticleDOI
RTSim: A Cycle-Accurate Simulator for Racetrack Memories
TL;DR: RTSim, an open source cycle-accurate memory simulator that enables performance evaluation of the domain-wall-based racetrack memories and the skyrmions-based RTMs is proposed, developed in collaboration with physicists and computer scientists.