Fernando Muñoz Chavero

Bio: Fernando Muñoz Chavero is an academic researcher from University of Seville. The author has contributed to research in topics: Ultrasonic sensor & Switched capacitor. The author has an hindex of 5, co-authored 17 publications receiving 829 citations.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

Abstract: In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

Very low-voltage analog signal processing based on quasi-floating gate transistors

Abstract: A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.

Passive RFID-Based Inventory of Traffic Signs on Roads and Urban Environments

Abstract: This paper presents a system with location functionalities for the inventory of traffic signs based on passive RFID technology. The proposed system simplifies the current video-based techniques, whose requirements regarding visibility are difficult to meet in some scenarios, such as dense urban areas. In addition, the system can be easily extended to consider any other street facilities, such as dumpsters or traffic lights. Furthermore, the system can perform the inventory process at night and at a vehicle’s usual speed, thus avoiding interfering with the normal traffic flow of the road. Moreover, the proposed system exploits the benefits of the passive RFID technologies over active RFID, which are typically employed on inventory and vehicular routing applications. Since the performance of passive RFID is not obvious for the required distance ranges on these in-motion scenarios, this paper, as its main contribution, addresses the problem in two different ways, on the one hand theoretically, presenting a radio wave propagation model at theoretical and simulation level for these scenarios; and on the other hand experimentally, comparing passive and active RFID alternatives regarding costs, power consumption, distance ranges, collision problems, and ease of reconfiguration. Finally, the performance of the proposed on-board system is experimentally validated, testing its capabilities for inventory purposes.

Intelligent Containers Based on a Low-Power Sensor Network and a Non-Invasive Acquisition System for Management and Tracking of Goods

Abstract: This paper presents a prototype of a system for intermodal freight transport with electronics management of goods. The system is based on low-power wireless networks connecting intelligent containers. The proposed intelligent container can be configured with different types of sensors inside. With the objective to preserve the sealing of the container, the data collected inside the container are transmitted through a metal communication channel based on ultrasonic techniques. Outside the container, the implemented system is composed by a long range and low-power scalable wireless network. Finally, a management subsystem has been designed for tracking, monitoring, and alarm reporting.

Subsampling Receivers with Applications to Software Defined Radio Systems

Abstract: Este trabajo de tesis propone la utilizacion sistemas basados en submuestreo como una alternativa para la implementacion de la etapa de down-conversion de los receptores de radio frecuencia (RF) empleados para aplicaciones multi-estandar y SDR (Software Defined Radio). El objetivo principal sera el de optimizar el diseno en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el numero de componentes al minimo es clave cuando un mismo receptor procesa diferentes estandares de comunicacion, las arquitecturas basadas en submuestreo han sido seleccionadas, donde la reusabilidad de los componentes empleados es posible, asi como la reduccion de los costes totales de los receptores de comunicacion y de los equipos de certificacion que emplean estas arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topologia del receptor. Como la idea de la tecnologia SDR es implementar todas las funcionalidades del receptor (filtrado, amplificacion) en el dominio digital, el convertidores analogico-digital (ADC) debera estar localizado en la cadena de recepcion lo mas cerca posible a la antena, siendo el objetivo final el convertir la senal directamente de RF a digital. Sin embargo, con los actuales ADC no es posible implementar esta idea debido al alto ancho de banda que necesitarian sin perder resolucion para cubrir las especificaciones de los estandares de comunicaciones inalambricas. Por tanto, los sistemas basados en submuestreo se presentan como la opcion mas adecuada para implementar este tipo de sistemas debido a que pueden muestrear la senal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la eleccion de la frecuencia de muestreo. De este modo, los requerimientos del ADC seran relajados ya que, usando estas arquitecturas, este componente procesara la senal a frecuencias intermedias. Una vez se han introducido los conceptos principales de las tecnicas de submuestreo, esta tesis doctoral presenta el diseno de una tarjeta de adquisicion de datos basada en submuestreo con la finalidad de ser implementada como un receptor de test y certificacion de banda ancha. El sistema propuesto proporciona una alta resolucion para un elevado ancho de banda, a partir del uso de un S&H de bajo jitter y de un convertidor analogico digital ADC que trabaja a frecuencias intermedias. El sistema es implementado usando dispositivos comerciales en una placa de circuito impreso disenada y fabricada, y cuya caracterizacion experimental muestra una resolucion de mas 8 bits para un ancho de banda analogico de 20 MHz. Concretamente, la resolucion medida sera mayor de 9 bits hasta una frecuencia de entrada de 2.9 GHz y mayor de 8 bits para una frecuencia de entrada de hasta 6.5 GHz, lo cual resulta suficiente para cubrir los requerimientos de la mayor parte de los actuales estandares de comunicaciones inalambricas (GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX). Sin embargo, los receptores basados en submuestreo presentan algunos importantes inconvenientes, como son adicionales fuentes de ruido (jitter y plegado de ruido termico) y una dificultad anadida para implementarlo en escenarios multi-banda y no lineales. Acerca del plegado de ruido en la banda de interes, esta tesis propone el uso de una tecnica basada en una arquitectura de reloj multiple con el objetivo de aumentar la resolucion y cubrir un numero mayor de estandares para su test y certificacion. Empleando una frecuencia de muestreo mayor para el caso del S&H, se conseguira reducir este efecto, aumentando la resolucion en aproximadamente 0.5-1 bit respecto al caso de solo usar una fuente de reloj. Las expresiones teoricas de esta mejora son desarrolladas y presentadas en esta tesis, siendo posteriormente corroboradas de modo experimental. Por otra parte, esta tesis tambien propone novedosas tecnicas para la aplicacion de estos sistemas de submuestreo en entornos multi-banda y no lineales, los cuales presentan desafios adicionales por el hecho de existir la posibilidad de solapamiento entre la senal de interes y los otros canales de comunicacion, asi como de solapamiento con sus armonicos. De este modo, esta tesis extiende el uso de los sistemas basados en submuestreo para este tipo de entornos, proponiendo tecnicas para la eleccion de la frecuencia optima de muestreo que evitan el solapamiento entre senales, a la vez que consiguen incrementar la resolucion del receptor. Finalmente, se presentara la optimizacion en cuanto a caracteristicas de ruido de un receptor concreto para aplicaciones de banda dual en entornos no lineales. Dicho receptor estara basado en las tecnicas de reloj multiple presentadas anteriormente y en una estructura de multi-filtro entre el S&H y el ADC. El sistema disenado podra emplearse para diversas aplicaciones a ambos lados de la cadena de comunicacion, tal como en receptores de deteccion de espectro para radio cognitiva, o implementando el bucle de realimentacion de un transmisor para la linealizacion de amplificadores de potencia. Por tanto, la presente tesis doctoral cuenta con tres contribuciones diferenciadas. La primera de ellas es la dedicada al diseno de un prototipo de recepcion multi-estandar basado en submuestreo para aplicaciones de test y certificacion. La segunda aportacion es la dedicada a la optimizacion de las especificaciones de ruido a partir de las tecnicas presentadas basadas en reloj multiple. Por ultimo, la tercera contribucion principal es la relacionada con la extension de este tipo de tecnicas a sistemas multi-banda en entornos no lineales. Todas estas contribuciones han sido estudiadas teoricamente y experimentalmente validadas.

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

Abstract: An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Abstract: An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

Digital and analog communication systems

Abstract: Add this article to private library Remove from private library Submit corrections to this record View record in the new ADS The book presents an introductory treatment of digital and analog communication systems with emphasis on digital systems. Attention is given to the following topics: systems and signal analysis, random signal theory, information and channel capacity, baseband data transmission, analog signal transmission, noise in analog communication systems, digital carrier modulation schemes, error control coding, and the digital transmission of analog signals. Bibtex entry for this abstract Preferred format for this abstract

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

Abstract: An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wireless power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30- μA stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18- μm CMOS and occupies 13.47 mm2. Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy (> 92%) within 0.8 s.

A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications

Abstract: This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 $\mu$ m CMOS process and consumes 32 $\mu$ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.