Here, we report advanced materials and devices that enable high-efficiency mechanical-to-electrical energy conversion from the natural contractile and relaxation motions of the heart, lung, and diaphragm, demonstrated in several different animal models, each of which has organs with sizes that approach human scales. A cointegrated collection of such energy-harvesting elements with rectifiers and microbatteries provides an entire flexible system, capable of viable integration with the beating heart via medical sutures and operation with efficiencies of ∼2%. Additional experiments, computational models, and results in multilayer configurations capture the key behaviors, illuminate essential design aspects, and offer sufficient power outputs for operation of pacemakers, with or without battery assist.

https://www.pnas.org/content/pnas/111/5/1927.full.pdf

Conformal piezoelectric energy harvesting and storage from motions of the heart, lung, and diaphragm

This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

An MOS transistor model for analog circuit design

The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.

/pdf/tradeoffs-and-optimization-in-analog-cmos-design-2vmcctfb10.pdf

Tradeoffs and Optimization in Analog CMOS Design

Pythium insidiosum: an overview.

Significant bone microarchitecture impairment in premenopausal women with active celiac disease

A synchronous polarimeter was set up for the measurement of
small rotation angles of the polarization plane of light. The
polarimeter is based on a polarizer–Faraday modulator–analyzer
structure with a synchronous detection scheme, which produces a linear
system response. The theoretical background is studied, and the
system performance is investigated experimentally. We achieved an
accuracy of the order of 10-4 deg, or 5 mg/dl of glucose
in a 1-cm light path.

Precision synchronous polarimeter with linear response for the measurement of small rotation angles.

There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting in-vivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum . The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5  $\mu$ m CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88  $\mu$ V $_{\text{rms}}$ , the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system.

/pdf/current-efficient-preamplifier-architecture-for-cmrr-3d1msa8o4d.pdf

Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications

Low Power Analog CMOS for Cardiac Pacemakers

Power reduction is a central priority in battery-powered medical implantable devices, particularly pacemakers, to either increase battery lifetime or decrease size using a smaller battery. Low Power Analog CMOS for Cardiac Pacemakers proposes new techniques for the reduction of power consumption in analog integrated circuits. Our main example is the pacemaker sense channel, which is representative of a broader class of biomedical circuits aimed at qualitatively detecting biological signals. The first and second chapters are a tutorial presentation on implantable medical devices and pacemakers from the circuit designer point of view. This is illustrated by the requirements and solutions applied in our implementation of an industrial IC for pacemakers. There from, the book discusses the means for reduction of power consumption at three levels: base technology, power-oriented analytical synthesis procedures and circuit architecture. At the technology level, we analyze the impact that the application of the fully depleted silicon-on-insulator (FD SOI) technology has on this kind of analog circuits. The basic building block levels as well as the system level (pacemaker sense channel) are considered. Concerning the design technique, we apply a methodology, based on the transconductance to current ratio that exploits all regions of inversion of the MOS transistor. Various performance aspects of analog building blocks are modeled and a power optimization synthesis of OTAs for a given total settling time (including the slewing and linear regions) is proposed. At the circuit level, we present a new design approach of a class AB output stage suitable for micropower application. In our design approach, the usual advantages of the application of a class AB output stage are enhanced by the application of a transconductance multiplication effect. These techniques are tested in experimental prototypes of amplifiers and complete pacemaker sense channel implementations in SOI and standard bulk CMOS technologies. An ultra low consumption of 110 nA (0.3 mW) is achieved in a FD SOI sense channel implementation. Though primarily addressed to the pacemaker system, the techniques proposed are shown to have application in other contexts where power reduction is a main concern.

Fernando Silveira

Papers

Significant bone microarchitecture impairment in premenopausal women with active celiac disease

Precision synchronous polarimeter with linear response for the measurement of small rotation angles.

Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications

Low Power Analog CMOS for Cardiac Pacemakers

Low Power Analog CMOS for Cardiac Pacemakers : Design and Optimization in Bulk and SOI Technologies