Fernando Silveira

Bio: Fernando Silveira is an academic researcher from University of the Republic. The author has contributed to research in topics: CMOS & Transistor. The author has an hindex of 15, co-authored 128 publications receiving 1364 citations.

General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters

Abstract: Energy loss due to top/bottom plate parasitic capacitances is one of the factors determining the efficiency of integrated switched capacitor DC/DC converters. This loss is particularly significant when MOS gate or deep trench capacitors are used. We propose a technique for top/bottom-plate charge recycling that can be applied with low overhead independently of the converter architecture. Two examples of application of the technique are presented. First, it is shown how the technique can be applied to any converter by transforming it to an interleaved implementation. This approach is demonstrated in a series-parallel 1/3 down converter achieving a maximum load power of 240 $\mu\text{W}$ . Simulation results show an improvement of 7% in the efficiency by decreasing the top/bottom-plate parasitic capacitance losses by 52%. The second example considers an architecture where the proposed technique can be directly applied without additional transformations of the converter implementation. It is a ring modular architecture converter, which was fabricated in a 130 nm CMOS process. An efficiency improvement of up to 4% was achieved in measurements by reducing the top/bottom plate losses by 70%, thus reaching an outstanding efficiency of 80.6% at a conversion ratio of 2/3 and a maximum load power of 2.2 mW.

Perspectives of TFETs for low power analog ICs

Abstract: In this paper we show that tunnel field effect transistors (TFETs) biased in the subthreshold region promise several advantages for low-power/high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption). Analytical and TCAD models for graphene nano-ribbon (GNR) and InAs/GaSb nanowire TFETs are employed, respectively, for the first time in subthreshold analog circuit examples using the g m /I d integrated circuit (IC) design technique. From comparison of these TFET technologies with traditional FETs it is observed that due to the higher currents per unit gate width at low voltage for TFETs, smaller, higher speed, and lower power analog circuits are enabled.

Average Power Consumption Breakdown of Wireless Sensor Network Nodes Using IPv6 over LLNs

Abstract: This paper presents a simple but still powerful approach for the analysis of the average power consumption of a sensor node using the IPv6 over Low power and Lossy Networks (LLN) stack, which is one of the most widely adopted and promising communication stacks. Power consumption is broken down according to the node states (i.e. CPU, IRQ, LPM, Tx, Rx) and according to the network protocols (e.g. CoAP, RPL, 6LoWPAN, Contiki MAC), identifying the relative weight of each protocol in the total energy consumption for several configurations. Results show that the Low Power Listening (LPL) mechanism of the radio duty cycling layer and RPL control messages have the highest impact on the total energy consumption, while the application's report rate has a very low impact for periods over 60 seconds.

MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design

Abstract: Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions.

Design of a micropower signal conditioning circuit for a piezoresistive acceleration sensor

Abstract: The design and test of a micropower signal conditioning circuit for a piezoresistive accelerometer is presented. The circuit is intended for sensing human body motion in rate-adaptive cardiac pacemakers. A strategy is proposed to allow handling of the piezoresistive sensor with the desired level of consumption. Experimental results show the fabricated circuit is able to measure accelerations in the range from 0.04 g to 0.34 g with a total consumption of less than 3 /spl mu/A with supply voltages down to 2 V.

Conformal piezoelectric energy harvesting and storage from motions of the heart, lung, and diaphragm

Abstract: Here, we report advanced materials and devices that enable high-efficiency mechanical-to-electrical energy conversion from the natural contractile and relaxation motions of the heart, lung, and diaphragm, demonstrated in several different animal models, each of which has organs with sizes that approach human scales. A cointegrated collection of such energy-harvesting elements with rectifiers and microbatteries provides an entire flexible system, capable of viable integration with the beating heart via medical sutures and operation with efficiencies of ∼2%. Additional experiments, computational models, and results in multilayer configurations capture the key behaviors, illuminate essential design aspects, and offer sufficient power outputs for operation of pacemakers, with or without battery assist.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

An MOS transistor model for analog circuit design

Abstract: This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

Tradeoffs and Optimization in Analog CMOS Design

Abstract: The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.