Here, we report advanced materials and devices that enable high-efficiency mechanical-to-electrical energy conversion from the natural contractile and relaxation motions of the heart, lung, and diaphragm, demonstrated in several different animal models, each of which has organs with sizes that approach human scales. A cointegrated collection of such energy-harvesting elements with rectifiers and microbatteries provides an entire flexible system, capable of viable integration with the beating heart via medical sutures and operation with efficiencies of ∼2%. Additional experiments, computational models, and results in multilayer configurations capture the key behaviors, illuminate essential design aspects, and offer sufficient power outputs for operation of pacemakers, with or without battery assist.

https://www.pnas.org/content/pnas/111/5/1927.full.pdf

Conformal piezoelectric energy harvesting and storage from motions of the heart, lung, and diaphragm

This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

An MOS transistor model for analog circuit design

The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.

/pdf/tradeoffs-and-optimization-in-analog-cmos-design-2vmcctfb10.pdf

Tradeoffs and Optimization in Analog CMOS Design

Pythium insidiosum: an overview.

This article presents a design methodology for the most simple cascode transistor's bias circuit, i.e. a diode-connected transistor, valid from weak to strong inversion. By taking advantage of a compact MOS transistor model, we show how the circuit can be easily designed to precisely fix the drain voltage of the cascoded transistor just above its saturation voltage. Test circuits were manufactured in a 0.35μm CMOS technology in order to test the design methodology under different operation regions (weak, moderate and strong inversion) and for long and short channel transistors. Standard deviation in measured drain voltage of the cascoded transistor is below 3% of its mean.

Bias circuit design for low-voltage cascode transistors

In this paper, 32 kHz crystal oscillators operating with only 60 mV supply are presented. Two implementations based on a Schmitt trigger circuit for two different crystals were designed and experimentally characterized. The circuits require 45 $\mu \text{m}\,\,\times74\,\,\mu \text{m}$ and 78 $\mu \text{m}\,\,\times83\,\,\mu \text{m}$ , respectively, within a 130 nm CMOS process. The power consumptions of the oscillators are 2.26 nW and 15 nW and the temperature stabilities attained are 62 ppm (25-62°C) and 50 ppm (5-62°C), respectively. The dependence on the supply voltage of the current consumption, fractional frequency, start-up time and oscillation amplitude were measured. The Allan deviation is 30 ppb for both oscillators.

/pdf/ultra-low-voltage-cmos-crystal-oscillators-42dwthpcw5.pdf

Ultra-Low-Voltage CMOS Crystal Oscillators

A new class AB output stage is presented which extends a family of recently proposed stages based on current mirrors without requiring extra-compensation capacitances. In-depth circuit analysis also shows the significant advantage of such stages for low-power consumption and leads to the derivation of an optimum design strategy. Experimental realizations are described, in particular a micropower amplifier for cardiac pacemaker application.

/pdf/analysis-and-design-of-a-family-of-low-power-class-ab-543rr1w0wc.pdf

Analysis and Design of a Family of Low-Power Class AB Operational Amplifiers

In this paper, a technique of digitally assisted RF detectors with variability compensation is proposed It enables the ability to obtain a high dynamic-range linear-in-dB characteristic with a small footprint Digital assistance is used to correct for a nonlinear characteristic and to perform a self-calibration In state-of-the-art CMOS RF systems-on-chip (SoCs), the digital capabilities required for this technique would not represent an overhead for the design, as they are already available The self-calibration compensates for the process variability relying on internal dc measurements and statistical information derived from the statistical models provided by the foundry This technique would benefit SoCs, which implement built-in self test or built-in self calibration by enabling multiple high dynamic-range internal RF measurements, while complying with tight area and power budgets A proof-of-concept detector cell is presented in a 90-nm CMOS process, which provides a maximum linearity error of $\pm {\hbox{15 dB}}$ and a 33-dB dynamic range at 2 GHz after digital correction The circuit occupies an area of ${\hbox{0004 mm}}^{2}$ and consumes a maximum of ${\hbox{240-}}\mu{\hbox{A}}$ from a 12-V supply The results are confirmed by measurements performed on ten samples

Digitally Assisted CMOS RF Detectors With Self-Calibration for Variability Compensation

Memoria presentada por Rafaella Fiorelli Martegani para optar al grado de Doctora por la Universidad de Sevilla y la Universidad de la Republica.

/pdf/an-all-inversion-region-gm-id-based-design-methodology-for-4fvt7yv41a.pdf

Fernando Silveira

Papers

Bias circuit design for low-voltage cascode transistors

Ultra-Low-Voltage CMOS Crystal Oscillators

Analysis and Design of a Family of Low-Power Class AB Operational Amplifiers

Digitally Assisted CMOS RF Detectors With Self-Calibration for Variability Compensation

An all-inversion-region gm/ID based design methodology for radiofrequency blocks in CMOS nanometer technologies