Filip Tavernier

Bio: Filip Tavernier is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Photodiode. The author has an hindex of 13, co-authored 63 publications receiving 494 citations. Previous affiliations of Filip Tavernier include Universidade Federal do Rio Grande do Sul & CERN.

High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS

Abstract: The design and measurement of two optical receivers with integrated photodiode in 130 nm CMOS is presented. The low bandwidth, which is typical for photodiodes in CMOS technologies, is circumvented by a differential photodiode topology on the one hand and by including an optimized equalizer in the receiver chain on the other hand. The low responsivity of a CMOS photodiode is compensated by a very low-noise design for the differential TIA. The disadvantage of such a low-noise design is its high power consumption. Therefore, a design strategy is presented where part of the circuit is biased in weak inversion. Doing so, the power consumption is decreased from 138 mW for the standard design to only 74.16 mW. Both designs are measured optically with 850 nm modulated light and are able to operate at 4.5 Gbit/s with a BER lower than 10-12. The sensitivities for this BER and speed are - 3.8 dBm and -3.4 dBm respectively. The receivers even work up to 5 Gbit/s for BER values around 10-9.

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Abstract: This paper presents a 1.25-GS/s 7-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS

Abstract: This article presents a 5-GS/s 12-b passive-sampling $8\times $ -interleaved hybrid analog-to-digital converter (ADC) that achieves a low-frequency SFDR/SNDR of 75.2/62.4 dB and a Nyquist SFDR/SNDR of 65.4/58.5 dB. A significant power reduction while attaining a bandwidth in excess of 6 GHz and a high spectral purity are enabled by: 1) an on-chip terminated very fast settling buffer-less input front end; 2) an on-chip clock chain with as low as 11-fs added jitter; 3) an asynchronous three-stage pipelined-successive approximation register (SAR) sub-ADC; and 4) on-chip co-designed analog–digital calibrations deal with sub-ADC and time-interleaving (TI) artifacts to achieve the desired spectral performance levels. The 28-nm bulk CMOS prototype chip occupies a total area of 4.56 mm2 with a core area of 1.76 mm2 and consumes 158.6 mW from a 1-V supply, leading to the Nyquist figure of merits of Schreier (FoMS) and Walden (FoMW) of 160.5 dB and 46.1 fJ/conversion step, respectively.

A 119dB Dynamic Range Charge Counting Light-to-Digital Converter For Wearable PPG/NIRS Monitoring Applications

Abstract: This paper presents a low power, high dynamic range (DR), reconfigurable light-to-digital converter (LDC) for photoplethysmogram (PPG), and near-infrared spectroscopy (NIRS) sensor readouts. The proposed LDC utilizes a current integration and a charge counting operation to directly convert the photocurrent to a digital code, reducing the noise contributors in the system. This LDC consists of a latched comparator, a low-noise current reference, a counter, and a multi-function integrator, which is used in both signal amplification and charge counting based data quantization. Furthermore, a current DAC is used to further increase the DR by canceling the baseline current. The LDC together with LED drivers and auxiliary digital circuitry are implemented in a standard 0.18 μm CMOS process and characterized experimentally. The LDC and LED drivers consume a total power of 196 μW while achieving a maximum 119 dB DR. The charge counting clock, and the pulse repetition frequency of the LED driver can be reconfigured, providing a wide range of power-resolution trade-off. At a minimum power consumption of 87 μW, the LDC still achieves 95 dB DR. The LDC is also validated with on-body PPG and NIRS measurement by using a photodiode (PD) and a silicon photomultiplier (SIPM), respectively.

High-Speed Optical Receivers with Integrated Photodiode in Nanoscale CMOS

Abstract: Introduction.- Optical communication - A high-level perspective.- From light to electrical current - The photodiode.- From current to voltage - The transimpedance amplifier.- Increasing the speed - The equalizer.- Towards a rail-to-rail voltage - The post amplifier.- Chip implementations.- Conclusions.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

Abstract: This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$ 16 dB Return Loss Over 10 GHz Bandwidth

Abstract: A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of <-16 dB up to 10 GHz a 40 mum times 40 mum T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 mum times 360 mum. In addition to the transmitter design, guidelines for the T-coil design are presented.

Addressing link-level design tradeoffs for integrated photonic interconnects

Abstract: Integrated photonic interconnects have emerged recently as a potential solution for relieving on-chip and chip-to-chip bandwidth bottlenecks for next-generation many-core processors. To help bridge the gap between device and circuit/system designers, and aid in understanding of inherent photonic link tradeoffs, we present a set of link component models for performing interconnect design-space exploration connected to the underlying device and circuit technology. To compensate for process and thermal-induced ring resonator mismatches, we take advantage of device and circuit characteristics to propose an efficient ring tuning solution. Finally, we perform optimization of a wavelength-division-multiplexed link, demonstrating the link-level interactions between components in achieving the optimal degree of parallelism and energy-efficiency.

Superior Plasmonic Photodetectors Based on Au@MoS2 Core-Shell Heterostructures.

Abstract: Integrating plasmonic materials into semiconductor media provides a promising approach for applications such as photosensing and solar energy conversion The resulting structures introduce enhanced light–matter interactions, additional charge trap states, and efficient charge-transfer pathways for light-harvesting devices, especially when an intimate interface is built between the plasmonic nanostructure and semiconductor Herein, we report the development of plasmonic photodetectors using Au@MoS2 heterostructures—an Au nanoparticle core that is encapsulated by a CVD-grown multilayer MoS2 shell, which perfectly realizes the intimate and direct interfacing of Au and MoS2 We explored their favorable applications in different types of photosensing devices The first involves the development of a large-area interdigitated field-effect phototransistor, which shows a photoresponsivity ∼10 times higher than that of planar MoS2 transistors The other type of device geometry is a Si-supported Au@MoS2 heterojuncti