Filipe D. Baumgratz

Bio: Filipe D. Baumgratz is an academic researcher from Universidade Federal do Rio Grande do Sul. The author has contributed to research in topics: Noise figure & Wideband. The author has an hindex of 4, co-authored 11 publications receiving 37 citations. Previous affiliations of Filipe D. Baumgratz include Katholieke Universiteit Leuven.

A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS

Abstract: A 130 nm CMOS wideband (0.2 to 3.3 GHz) low-noise variable-gain amplifier (LNVGA) with two active baluns working for phase cancellation is presented herein. The LNVGA aims for a wide gain tuning range which avoids signal compression, while enabling a low noise figure. This figure is kept low by the first stage of the LNVGA, whereas the second stage provides the gain variation. The second stage is able to deliver a wide gain tuning range thanks to the utilization of the phase cancellation technique, which is implemented by two active baluns. Since the phase cancellation technique strongly relies on the balun output balancing, a low-imbalance active balun topology is being herein proposed, analyzed in detail, designed, and tested. This new LNVGA design achieves a gain tuning range of 45 dB, a noise figure of 3.4 dB, and dissipates 19 mW in the maximum gain condition. The circuit was fabricated in 130-nm CMOS with a 1.2-V supply.

40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor

Abstract: A 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra transistors. Additionally, a modified charge-sharing bandpass filter with cross-connected transconductors to boost Q-factor is proposed and discussed. The highest voltage gain achieved by the receiver (RX) is 30 dB. The RX noise figure is 3.3 dB at the maximum gain, while the IIP3 is −2.5 dBm at 1 GHz. The area of the receiver is very competitive for the wide band considered, merely 0.137 mm2. The RX and clock generation circuitry drain 25 mA from a 0.9-V supply.

A 0.4–3.3 GHz low-noise variable gain amplifier with 35 dB tuning range, 4.9 dB NF, and 40 dBm IIP2

Abstract: This work presents a low-noise variable gain amplifier (LNVGA) in which the IIP2 is very high, and the gain control is applied to improve the system dynamic range, even with the limitations of the CMOS technology. Two stages compose the LNVGA, a low-noise amplifier, that keeps the noise figure (NF) at low values, and a variable voltage attenuator (VVA), that provides the gain variation. We have applied on the VVA the phase cancellation technique, in which the addition of two out-of-phase signals controls the gain. This technique provides a large gain tuning range only if the paths of the two signalsto be added are well balanced; hence, a precise 180 degrees phase difference is required. In this desing we propose an active balun with small imbalance, which creates those signals. The LNVGA was implemented in 130 nm CMOS with a 1.2 V supply. The measurement results show a 35 dB gain tuning range, varying from 10 to − 25 dB, a 4.9 dB minimum NF, a − 10 dBm IIP3, and an IIP2 as high as + 40 dBm.

Review on the Evolution of Low-power and Highly-linear Time-to-Digital Converters - TDC

Abstract: Time-to-digital converters (TDC) have been widely used in all-digital phase-locked loops (ADPLL). However, the TDC non-linearity and resolution have negatively impacted the ADPLL performance. A better integration between the TDC and ADPLL would improve the performance of the ADPLL, with a minimum increase in power consumption. This paper addresses the main issues in TDC design providing an overview of published architectures. In particular, the evolution of resolution and non-linearity indicators will be reviewed in detail, since they are the most important figures for proper integration of TDCs in ADPLLs.

Wideband Low Noise Variable Gain Amplifier

Abstract: A low noise variable gain amplifier (LNVGA) is fully designed for operation over a wideband. Since a low noise figure (NF) and a high 1 dB compression point (P1dB), i.e. large dynamic range, is difficult to achieve in CMOS technology, gain controllability is exploited to increase the overall system dynamic range. The LNVGA is composed by a low noise amplifier (LNA) stage and a voltage variable attenuator (VVA) stage. The former aims to keep the NF low, and the latter aims to provide a very large gain variation. Also, an output buffer is used to allow for measurement with 50 O probes. In addition, a novel Active Balun topology is proposed which achieves competitive results for magnitude imbalance and phase imbalance. The LNVGA simulation results show a gain control range of 47.7 dB, its voltage gain varies from −26.7 dB to 21 dB, the minimum NF is 3.43 dB, the IIP3 is −4.6 dBm, and a band of operation from 200 MHz to 3.5 GHz.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

Abstract: This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells

Abstract: Transistor sizing of sub-threshold standard cells for digital ultra-low power systems is a very challenging task because robustness has to be considered as an important design objective in addition to the competing resources power consumption and propagation delay. In this paper we regard this task as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold CMOS logic standard cells. Optimization results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.

A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS

Abstract: A 130 nm CMOS wideband (0.2 to 3.3 GHz) low-noise variable-gain amplifier (LNVGA) with two active baluns working for phase cancellation is presented herein. The LNVGA aims for a wide gain tuning range which avoids signal compression, while enabling a low noise figure. This figure is kept low by the first stage of the LNVGA, whereas the second stage provides the gain variation. The second stage is able to deliver a wide gain tuning range thanks to the utilization of the phase cancellation technique, which is implemented by two active baluns. Since the phase cancellation technique strongly relies on the balun output balancing, a low-imbalance active balun topology is being herein proposed, analyzed in detail, designed, and tested. This new LNVGA design achieves a gain tuning range of 45 dB, a noise figure of 3.4 dB, and dissipates 19 mW in the maximum gain condition. The circuit was fabricated in 130-nm CMOS with a 1.2-V supply.

Wideband 28-nm CMOS Variable-Gain Amplifier

Abstract: This paper discusses a wideband variable-gain amplifier (VGA) implemented in a 28-nm FDSOI CMOS technology. This VGA employs optimal-biasing and differential large-signal pre-distortion linearizations that operate over all gain settings and over its frequency range. The 0.4-to-4-GHz VGA, which consists of its core circuit and an output buffer, exhibits a wideband gain ranging from 4.6 to 12 dB in 1-dB steps and an input return loss higher than 10 dB while demonstrating a worst-case IM3 of −54 dBm across the gain range at ~0-dBm output power and noise figures from 3 to 5.9 dB at 12 dB gain. The VGA and buffer consume 15 mA and 60 mA from a 1.5 V supply, respectively. The total chip area, including the bond pads, is ${1\times 1\,\text {mm}^{2}}$ .

Multiband LNAs for Software-Defined Radios: Recent Advances in the Design of Multiband Reconfigurable LNAs for SDRs in CMOS, Microwave Integrated Circuits Technology

Abstract: The last decade has witnessed an increasing number of wireless standards for civil, military, and space communications. Along with the advances in integrated circuit (IC) technologies and the ever-growing requirements of high data rates, next-generation radios are expected to operate over multiple frequency bands. For example, carrier aggregation is used in LTE-Advanced radios to increase the bandwidth. However, it is challenging for traditional radios to operate over multiple frequency bands. In response to this, software-defined radios (SDRs) have been proposed to handle multiple bands through reconfiguration. They can adapt carrier frequency, transmission bandwidth, modulation, and encoding schemes by modifying digital signal processing (DSP) software algorithms [1]. In contrast to SDR, legacy communication systems are approaching their capability limits. They usually operate on a single band and require dedicated hardware. Thus, SDR is a promising radio technology to increase the flexibility of radio devices and reduce hardware and manufacturing costs, chip size, and power consumption [2].