F
Filipp Akopyan
Researcher at IBM
Publications - 25
Citations - 6041
Filipp Akopyan is an academic researcher from IBM. The author has contributed to research in topics: TrueNorth & Neuromorphic engineering. The author has an hindex of 16, co-authored 25 publications receiving 4683 citations. Previous affiliations of Filipp Akopyan include Cornell University.
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Journal ArticleDOI
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla,John V. Arthur,Rodrigo Alvarez-Icaza,Andrew S. Cassidy,Jun Sawada,Filipp Akopyan,Bryan L. Jackson,Nabil Imam,Chen Guo,Yutaka Nakamura,Bernard Brezzo,Ivan Vo,Steven K. Esser,Rathinakumar Appuswamy,Brian Taba,Arnon Amir,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +19 more
TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
Journal ArticleDOI
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan,Jun Sawada,Andrew S. Cassidy,Rodrigo Alvarez-Icaza,John V. Arthur,Paul A. Merolla,Nabil Imam,Yutaka Nakamura,Pallab Datta,Gi-Joon Nam,Brian Taba,Michael P. Beakes,Bernard Brezzo,Jente B. Kuang,Rajit Manohar,William P. Risk,Bryan L. Jackson,Dharmendra S. Modha +17 more
TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
Proceedings ArticleDOI
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm
TL;DR: This work fabricated a key building block of a modular neuromorphic architecture, a neurosynaptic core, with 256 digital integrate-and-fire neurons and a 1024×256 bit SRAM crossbar memory for synapses using IBM's 45nm SOI process, leading to ultra-low active power consumption.
Proceedings ArticleDOI
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
Andrew S. Cassidy,Paul A. Merolla,John V. Arthur,Steve K. Esser,Bryan L. Jackson,Rodrigo Alvarez-Icaza,Pallab Datta,Jun Sawada,Theodore M. Wong,Vitaly Feldman,Arnon Amir,Daniel D Ben Dayan Rubin,Filipp Akopyan,Emmett McQuinn,William P. Risk,Dharmendra S. Modha +15 more
TL;DR: A simple, digital, reconfigurable, versatile spiking neuron model that supports one-to-one equivalence between hardware and simulation and is implementable using only 1272 ASIC gates is developed.
Proceedings ArticleDOI
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core
John V. Arthur,Paul A. Merolla,Filipp Akopyan,Rodrigo Alvarez,Andrew S. Cassidy,Shyamal Suhana Chandra,Steven K. Esser,Nabil Imam,William P. Risk,Daniel D Ben Dayan Rubin,Rajit Manohar,Dharmendra S. Modha +11 more
TL;DR: A building block of a modular neuromorphic architecture, a neurosynaptic core that is fully configurable in terms of neuron parameters, axon types, and synapse states and its fully digital implementation achieves one-to-one correspondence with software simulation models.