Florinel G. Balteanu

Bio: Florinel G. Balteanu is an academic researcher from Skyworks Solutions. The author has contributed to research in topics: Amplifier & Signal. The author has an hindex of 18, co-authored 76 publications receiving 1209 citations. Previous affiliations of Florinel G. Balteanu include Conexant.

Apparatus and methods for envelope tracking

Abstract: Apparatus and methods for envelope tracking are disclosed. In one embodiment, a power amplifier system including a power amplifier and an envelope tracker is provided. The power amplifier is configured to amplify a radio frequency (RF) signal, and the envelope tracker is configured to control a supply voltage of the power amplifier using an envelope of the RF signal. The envelope tracker includes a buck converter for generating a buck voltage from a battery voltage and a digital-to-analog conversion (DAC) module for adjusting the buck voltage based on the envelope of the RF signal to generate the supply voltage for the power amplifier.

Quad-band GSM/GPRS/EDGE polar loop transmitter

Abstract: An enhanced data-rates for GSM evolution (EDGE) transmitter using a nonlinear GSM-type PA is presented. It is based on a novel polar loop architecture that employs separate feedback control of the amplitude and the phase of the output signal. With this approach, the problems with AM-to-PM as well as AM-to-AM of the nonlinear PA are essentially eliminated. In addition, this architecture allows for a large dynamic output power control range, as required by the GSM specification. The transmitter uses a standard I/Q interface and does not require the extraction of amplitude and phase modulation in the digital domain. The dual feedback loop ensures robust performance even under voltage-standing wave ratio variations without using an isolator. No external PA filtering is required to meet the transmitter noise in the receive band. The EDGE spectral mask is met with an rms error vector magnitude of <3% at 29 dBm at the antenna, corresponding to 2 dB above nominal maximum output power. There is no mode change between GMSK and EDGE, and the transmitter operates seamlessly in multislot Enhanced General Packet Radio Service. The polar modulation transmitter meets or exceeds the GSM-type approval requirements for both EDGE and GMSK in quad band (850/900/1800/1900 MHz).

Delta-sigma based dual-port modulation scheme and calibration techniques for similar modulation schemes

Abstract: PLL frequency synthesizers and their calibration techniques are described. The PLL frequency synthesizers are used to generate digital modulation of a carrier signal. A digital frequency divider in the feedback path of the loop has its division ratio controlled by a digital Δ-Σ modulator. The modulation of the carrier is achieved by applying a modulation signal to the input of the Δ-Σ modulator and to the input of the voltage-controlled oscillator of the PLL. The high frequency path and low frequency path of the modulation signal must be adjusted with respect to one another in order to obtain a good modulation. As the low frequency path can be accurately set, the calibration is performed only on the high frequency path. Digital calibration techniques for the high frequency path are described.

A 22 mW Bluetooth RF transceiver with direct RF modulation and on-chip IF filtering

Abstract: A +2 dBm Bluetooth transceiver in 0.5 /spl mu/m SiGe BiCMOS consumes 22 mW at 2 V. The transmitter uses a /spl Delta//spl Sigma/ synthesizer and on-chip VCO to directly modulate the carrier and settles to 30 ppm within 180 /spl mu/s. The single low-IF I/O receiver uses a 7th-order complex IF filter with tuning, distributed AGC and digital PLL demodulation.

A 43mW Bluetooth transceiver with -91dBm sensitivity

Abstract: A Bluetooth transceiver has -91dBm sensitivity while drawing 24mA from a 1.8V supply. The receiver has a low-IF path with 30dB image and 9dB co-channel rejection, 80dB of AGC, digital equalization and complex PLL demodulation. The transmitter uses direct two-point modulation and draws 18mA at +6dBm output power. The DS PLL settles in 100/spl mu/s. LDO regulators power the analog and digital sections.

All-digital PLL and transmitter for mobile phones

Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

An Improved Power-Added Efficiency 19-dBm Hybrid Envelope Elimination and Restoration Power Amplifier for 802.11g WLAN Applications

Abstract: A comparison of envelope elimination and restoration (EER) and envelope tracking (ET) is discussed and a "hybrid" wideband EER power amplifier (PA) for the WLAN 802.11g system is proposed. A 60% efficiency (the output envelope signal power/input dc power) DC-20-MHz wideband envelope amplifier is designed for wideband EER and wideband ET (WBET) applications. A design method is developed to optimize the efficiency of the envelope amplifier for a given peak-to-average ratio and average slew rate of the envelope signal. An experimental "hybrid" Class-E EER system shows an overall efficiency (modulated RF output power/envelope amplifier dc input power) of 36% and power-added efficiency (the modulated RF output power/envelope amplifier dc input power plus RF input power) of 28% for a WLAN 802.11g signal at 19-dBm (80 mW) output power at 2.4 GHz. Digital predistortion, time alignment, and memory effect mitigation are implemented. The measured 3% error vector magnitude exceeds the 802.11g specification for 5% for a 54-Mb/s modulation signal

Toward multistandard mobile terminals - fully integrated receivers requirements and architectures

Abstract: In the recent past, there has been an evolution in wireless communications toward multifunctions and multistandard mobile terminals. Reducing the number of external components to a minimum is key when the same mobile terminal has to process several different standards. Highly integrated solutions in low-cost silicon technologies are thus required. Zero-IF and low-IF receiver architectures are most suitable for a high level of integration. This paper presents a review of global system for mobile communications, universal mobile telecommunication system, Bluetooth, and wireless local area network (IEEE802.11a, b, g and HiperLAN2) standards, likely to all be present in the "universal" terminal of the future, enabling global roaming and wireless connectivity. The various standards are analyzed in order to find the optimal architecture and the building-block specifications for the receive section, with particular care to the RF front-end. State-of-the-art solutions are discussed, with emphasis on direct conversion CMOS implementations. A multistandard architecture for a fully-integrated CMOS receiver is proposed.

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

Abstract: This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.