Francisco Gamiz

Bio: Francisco Gamiz is an academic researcher from University of Granada. The author has contributed to research in topics: Electron mobility & Monte Carlo method. The author has an hindex of 36, co-authored 363 publications receiving 5098 citations. Previous affiliations of Francisco Gamiz include University of Glasgow & University of Seville.

On the enhanced electron mobility in strained-silicon inversion layers

Abstract: The recently reported large enhancement of the electron mobility in strained-Si inversion layers at large carrier concentrations cannot be easily explained: The strong carrier confinement in inversion layers removes the sixfold degeneracy of the conduction-band minima, much as tensile in-plane strain does, so that the effect of strain should become irrelevant at large sheet carrier densities. The problem is studied by calculating the electron mobility accounting for scattering with phonons and interface roughness. Surprisingly, the latter process is found to be significantly stronger in strained layers for a given interface roughness. Only the ad hoc assumption of increasingly smoother interfaces with increasing strain seems to explain the data.

Electron transport in strained Si inversion layers grown on SiGe-on-insulator substrates

Abstract: We show by simulation that electron mobility and velocity overshoot are greater when strained inversion layers are grown on SiGe-On-insulator substrates (strained Si/SiGe-OI) than when unstrained silicon-on-insulator (SOI) devices are employed. In addition, mobility in these strained inversion layers is only slightly degraded compared with strained bulk Si/SiGe inversion layers, due to the phonon scattering increase produced by greater carrier confinement. Poisson and Schroedinger equations are self-consistently solved to evaluate the carrier distribution in this structure. A Monte Carlo simulator is used to solve the Boltzmann transport equation. Electron mobility in these devices is compared to that in SOI inversion layers and in bulk Si/SiGe inversion layers. The effect of the germanium mole fraction x, the strained-silicon layer thickness, TSi, and the total width of semiconductor (Si+SiGe) slab sandwiched between the two oxide layers, Tw were carefully analyzed. We observed strong dependence of the e...

Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion

Abstract: The electron mobility in a double-gate silicon-on-insulator (DGSOI) device is studied as a function of the transverse effective field and silicon layer thickness. The contributions of the main scattering mechanisms (phonon scattering, surface roughness scattering due to both Si–SiO2 interfaces, and Coulomb interaction with the interface traps of both interfaces) are taken into account and carefully analyzed. We demonstrate that the contribution of surface scattering mechanisms is by no means negligible; on the contrary, it plays a very important role which must be taken into account when calculating the mobility in these structures. The electron mobility in DGSOI devices as Tw decreases is compared with the mobility in single-gate silicon-on-insulator structures (i) when only phonon scattering is considered, (ii) when the effect of surface-roughness scattering is taken into account, and (iii) when the contribution of Coulomb interaction with charges trapped at both interfaces is taken into consideration (...

Surface roughness at the Si–SiO2 interfaces in fully depleted silicon-on-insulator inversion layers

Abstract: The effect of surface roughness scattering on electron transport properties in extremely thin silicon-on-insulator inversion layers is carefully analyzed. It is shown that if the silicon layer is thin enough (thinner than 10 nm) the presence of the buried interface plays a very important role, both by modifying the surface roughness scattering rate due to the gate interface, and by itself providing a non-negligible scattering rate. The usual surface roughness scattering model in bulk silicon inversion layers is shown to overestimate the effect of the surface-roughness scattering due to the gate interface as a consequence of the minimal thickness of the silicon layer. In order to account for this effect, an improved model is provided. The proposed model allows the evaluation of the surface roughness scattering rate due to both the gate interface and the buried interface. Once the scattering rates are evaluated, electron mobility is calculated by the Monte Carlo method. The effect of the buried interface ro...

Semiconductor-On-Insulator Materials for Nanoelectronics Applications

Abstract: New semiconductor-on-insulator materials.- Physics of modern SemOI devices.- Diagnostics of the SOI devices.- Sensors and MEMS on SOI.

Device scaling limits of Si MOSFETs and their application dependencies

Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Opportunities and Challenges of Wireless Sensor Networks in Smart Grid

Abstract: The collaborative and low-cost nature of wireless sensor networks (WSNs) brings significant advantages over traditional communication technologies used in today's electric power systems. Recently, WSNs have been widely recognized as a promising technology that can enhance various aspects of today's electric power systems, including generation, delivery, and utilization, making them a vital component of the next-generation electric power system, the smart grid. However, harsh and complex electric-power-system environments pose great challenges in the reliability of WSN communications in smart-grid applications. This paper starts with an overview of the application of WSNs for electric power systems along with their opportunities and challenges and opens up future work in many unexploited research areas in diverse smart-grid applications. Then, it presents a comprehensive experimental study on the statistical characterization of the wireless channel in different electric-power-system environments, including a 500-kV substation, an industrial power control room, and an underground network transformer vault. Field tests have been performed on IEEE 802.15.4-compliant wireless sensor nodes in real-world power delivery and distribution systems to measure background noise, channel characteristics, and attenuation in the 2.4-GHz frequency band. Overall, the empirical measurements and experimental results provide valuable insights about IEEE 802.15.4-compliant sensor network platforms and guide design decisions and tradeoffs for WSN-based smart-grid applications.