An improved endoscopic device which is introduced into the intestinal tract of a living organism and which operates autonomously therein, adapted to obtain and store or transmit one or more types of data such as visual image data, laser autofluorescence data, or ultrasonic waveform data. In another aspect of the invention, an improved endoscopic device useful for implanting the aforementioned endoscopic smart probe is disclosed. In another aspect of the invention, apparatus for delivering agents including nanostructures, radionuclides, medication, and ligands is disclosed. In another aspect of the invention, apparatus for obtaining a biopsy of intestinal tissue is disclosed. In another aspect of the invention, apparatus for detecting the presence of one or more molecular species within the intestine is disclosed. Methods for inspecting and/or treating the interior regions of the intestinal tract using the aforementioned apparatus are also disclosed.

Endoscopic smart probe and method

The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.

A decade of reconfigurable computing: a visionary retrospective

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

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System-level power optimization: techniques and tools

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.

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Multiprocessor System-on-Chip (MPSoC) Technology

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.

Data and memory optimization techniques for embedded systems

From the Publisher:
This book grants the reader a comprehensive overview of the state-of-the-art in system-level memory management (data transfer and storage) related issues for complex data-dominated real-time signal and data processing applications. The authors introduce their own system-level data transfer and storage exploration methodology for data-dominated video applications. This methodology tackles the power and area reduction cost components in the architecture for this target domain, namely the system-level busses and the background memories. For the most critical tasks in the methodology, prototype tools have been developed to reduce the design time. To the researcher the book will serve as an excellent reference source, both for the overall description of the methodology and for the detailed descriptions of the system-level methodologies and synthesis techniques and algorithms. To the design engineers and CAD managers it offers an invaluable insight into the anticipated evolution of commercially available design tools as well as allowing them to utilize the book's concepts in their own research and development.

Custom Memory Management Methodology : Exploration of Memory Organisation for Embedded Multimedia System Design

A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors. The customized processor normally executes a sequence of a plurality of pre-customized routines, usually for which it has been optimized. To provide some flexibility for design changes and optimizations, a controller for monitoring the customized processor during execution of routines is provided to select one of a set of pre-customized processing interruption points and for switching context from the customized processor to the flexible processor at the interruption point. The customized processor can then be switched off and the flexible processor carries out a modified routine. By using sharable a data store, the context switch can be chosen at a time when all relevant data is in the sharable data store. This means that the flexible processor can pick up the modified processing cleanly. After the modified processing the flexible processor writes back new data into the data store and the customized processor can continue processing either where it left off or may skip a certain number of cycles as instructed by the flexible processor, before beginning processing of the new data.

Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors

A formalized method and a design system are described for part of the design decisions, related to memory, involved while designing an essentially digital device. The method and system determine an optimized memory organization starting from a representation of said digital device, the representation describing the functionality of the digital device and comprising data access instructions on basic groups, which are groups of scalar signals. The method and system determine optimized scheduling intervals of said data access instructions such that execution of said functionality with the digital device is guaranteed to be within a predetermined cycle budget, the determining of the optimized scheduling intervals comprising optimizing access conflicts with respect to an evaluation criterion related to the memory cost of said digital device. An optimized memory organization is selected in accordance with the optimized scheduling intervals and the optimized access conflicts.

A method for determining a storage-bandwidth optimized memory organization of an essentially digital device

A battery-powered computing system (20) including video decoding capability, particularly as pertinent to the H.263 standard, is disclosed. The system (20) includes a main integrated circuit (30) having an on-chip central processing unit (CPU) (32) and on-chip shared memory (33) for the temporary buffering of video image data that is retrieved and generated during the video decoding process. The CPU (32) is programmed to perform a combined P and B prediction process (46) upon a previously predicted P frame (PT-1), with accesses to internal buffers in shared memory (33) instead of to main memory (40). Preferably, inverse transform processes (48, 52) also access shared memory (33) rather than main memory (40). The combined P and B prediction process (46) preferably handles unrestricted motion vectors using edge pixels (Pedge) stored in an edge buffer (44e) in the on-chip memory (33), by modifying (58, 60) motion vector components (MVx, MVy) that point outside of the displayable video image, and retrieving the corresponding edge pixels (Pedge) from the edge buffer (44e) in this event. The on-chip memory (33) preferably also includes a buffer (NEWBFR) for storing current predicted P blocks, such that the previous predicted P frame (PT-1) and the current predicted P frame (PT) can share the same memory space (old/newframe). The power requirements of the video decoding process are thus much reduced, as memory accesses to large, off-chip, main memory (40) are limited.

Francky Catthoor

Papers

Custom Memory Management Methodology : Exploration of Memory Organisation for Embedded Multimedia System Design

Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors

A method for determining a storage-bandwidth optimized memory organization of an essentially digital device

Low power video decoder system with block-based motion compensation

Storage Management Programmable Process