Francois Krummenacher

Bio: Francois Krummenacher is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: CMOS & Switched capacitor. The author has an hindex of 30, co-authored 158 publications receiving 5199 citations. Previous affiliations of Francois Krummenacher include École Normale Supérieure & École Polytechnique.

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

Abstract: Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

Abstract: A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3- mu m p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD >

A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning

Abstract: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 ?m CMOS process. The design approach is based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range. PLL techniques, involving a 8.5 MHz controlled oscillator that matches a specific part of the filter, are used to realize on-chip automatic tuning. The complete circuit features 71 dB dynamic range and consumes only 16 mW from a single 5 V supply.

Pixel detectors with local intelligence: an IC designer point of view

Abstract: Scaling laws for the analog front end and related problems are discussed for detectors in the range from microstrips to pixel detectors. Design strategies for fast- and low-power building blocks (charge-sensitive preamplifier, shaper, discriminator and analog storage) are looked into. Merging of functions for minimal transistor counts, local analog storage versus digital-only output (trade-offs and limitations) and precision of and matching between readout elements are also discussed.

A model for /spl mu/-power rectifier analysis and design

Abstract: This paper proposes a linear two-port model for an N-stage modified-Greinacher full-wave rectifier. It predicts the overall conversion efficiency at low power levels where the diodes are operating near their threshold voltage. The output electrical behavior of the rectifier is calculated as a function of the received power and the antenna parameters. Moreover, the two-port parameter values are computed for particular input voltages and output currents for the complete N-stage rectifier circuit using only the measured I-V and C-V characteristics of a single diode. To validate the model a three-stage modified-Greinacher full-wave rectifier was realized in an silicon-on-sapphire (SOS) CMOS 0.5-/spl mu/m technology. The measurements are in excellent agreement with the values calculated using the presented model.

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

Abstract: In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

A low-power low-noise CMOS amplifier for neural recording applications

Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

Timepix, a 65k programmable pixel readout chip for arrival time, energy and/or photon counting measurements

Abstract: A novel approach for the readout of a TPC at the future linear collider is to use a CMOS pixel detector combined with some kind of gas gain grid. A first test using the photon counting chip Medipix2 with GEM or Micromegas demonstrated the feasibility of such an approach. Although this experiment demonstrated that single primary electrons could be detected the chip did not provide information on the arrival time of the electron in the sensitive gas volume nor did it give any indication of the quantity of charge detected. The Timepix chip uses an external clock with a frequency of up to 100 MHz as a time reference. Each pixel contains a preamplifier, a discriminator with hysteresis and 4-bit DAC for threshold adjustment, synchronization logic and a 14-bit counter with overflow control. Moreover, each pixel can be independently configured in one of four different modes: masked mode: pixel is off, counting mode: 1-count for each signal over threshold, TOT mode: the counter is incremented continuously as long as the signal is above threshold, and arrival time mode: the counter is incremented continuously from the time the first hit arrives until the end of the shutter. The chip resembles very much the Medipix2 chip physically and can be readout using slightly modified versions of the various existing systems. This paper presents the main features of the new design, electrical measurements and some first images.

FinFETs and Other Multi-Gate Transistors

Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.