Frank Hall Schmidt

Bio: Frank Hall Schmidt is an academic researcher. The author has contributed to research in topics: Reconfigurability. The author has an hindex of 1, co-authored 1 publications receiving 13 citations.

Fault tolerant design implementation on radiation hardened by design SRAM-Based FPGAs

Abstract: SRAM-based FPGAs are highly attractive for space applications due to their in-flight reconfigurability, decreased development time and cost, and increased design and testing flexibility. The Xilinx Virtex-5QV is the first commercially available Radiation Hardened By Design (RHBD) SRAM-based FPGA; however, not all of its internal components are hardened against radiation-induced errors. This thesis examines and quantifies the additional considerations and techniques designers should employ with a RHBD SRAM-based FPGA in a space-based processing system to achieve high operational reliability. Additionally, this work presents the application of some of these techniques to the embedded avionics design of the REXIS imaging payload on the OSIRIS-REx asteroid sample return mission.

Regolith X-Ray Imaging Spectrometer (REXIS) Aboard the OSIRIS-REx Asteroid Sample Return Mission

Abstract: The Regolith X-ray Imaging Spectrometer (REXIS) is the student collaboration experiment proposed and built by an MIT-Harvard team, launched aboard NASA’s OSIRIS-REx asteroid sample return mission. REXIS complements the scientific investigations of other OSIRIS-REx instruments by determining the relative abundances of key elements present on the asteroid’s surface by measuring the X-ray fluorescence spectrum (stimulated by the natural solar X-ray flux) over the range of energies 0.5 to 7 keV. REXIS consists of two components: a main imaging spectrometer with a coded aperture mask and a separate solar X-ray monitor to account for the Sun’s variability. In addition to element abundance ratios (relative to Si) pinpointing the asteroid’s most likely meteorite association, REXIS also maps elemental abundance variability across the asteroid’s surface using the asteroid’s rotation as well as the spacecraft’s orbital motion. Image reconstruction at the highest resolution is facilitated by the coded aperture mask. Through this operation, REXIS will be the first application of X-ray coded aperture imaging to planetary surface mapping, making this student-built instrument a pathfinder toward future planetary exploration. To date, 60 students at the undergraduate and graduate levels have been involved with the REXIS project, with the hands-on experience translating to a dozen Master’s and Ph.D. theses and other student publications.

A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter

Abstract: Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system generator based on the Zynq-7000 development board (ZYBO). The technique is compared, for reliability and hardware resources requirement, with triple modular redundancy (TMR), five modular redundancy (FMR) and the modified triplex–duplex architecture. Furthermore, radiation induced failures are emulated by switching all duplicated modules inputs to different signals, or to ground during simulation. The simulation results show that the proposed technique has 25% and 30%longer expected life compared to TMR and FMR techniques, respectively, and has the lowest hardware resource requirement compared to FMR and the modified triplex–duplex techniques.

A Review on SEU Mitigation Techniques for FPGA Configuration Memory

Abstract: Single event upset (SEU) has become one of the major threats to dependable application development targeted at safety systems in field programmable gate arrays (FPGAs). This article briefly reviews the mitigation techniques for SEUs in the configuration memory of SRAM-based FPGAs, as the configuration memory is highly susceptible to SEUs. Various reconfiguration methods are reviewed and the main focus is given to partial reconfiguration with error correction codes and scrubbing. It also covers the algorithmic and architectural changes which prevent or mitigates SEUs in the configuration memory bits dedicated for routing resources and logic resources. The major techniques are compared based on their SEU mitigation capability, area overhead, and delay.

Verification of fault tolerant techniques in finite state machines using simulation based fault injection targeted at FPGAs for SEU mitigation

Abstract: Field Programmable Gate Arrays (FPGA) are susceptible to soft errors due to the shrinkage of feature size and reduction in core voltage which reduces the critical charge required to change the state of a circuit element. To improve the reliability and availability of the FPGA based designs used in Nuclear Power Plants special care has to be taken against these emerging risks. In this paper, the effects of radiation on Finite State Machines (FSM) is reviewed and resource utilization and performance penalty are analyzed by using the fault tolerant techniques like Triple Modular Redundancy (TMR), Hamming-3 encoding and safe FSM synthesis. A novel scripting based fault injection technique is proposed for verifying the fault tolerant techniques at netlist level. The PREP3 state machine is used as a benchmark circuit in this paper. This work predominantly focuses on the practical use of fault tolerant techniques such as TMR, Error Detection and Correction by using Hamming-3 encoding for state register and Safe FSM implementation in live designs targeted at Nuclear Power Plants in India. The major objective of this work is to review the various field proven fault tolerant techniques targeted at FPGAs and develop a simple scalable methodology for verification of the same.