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Showing papers by "Fred Barlow published in 2001"


01 Jan 2001
TL;DR: Shin-Etsu as mentioned in this paper uses metal wires embedded in a matrix of polymeric material to make contact between metallized gold pads on the substrates via the embedded wires.
Abstract: Electronic packaging continues to produce denser systems. Currently chip packages have more than 1000 I/O, boards have 50-micron lines/spaces, and area array connectors with 1 mm pitch are readily available. To further increase system density, growth into the third dimension (z-axis) is required. However, stacked substrate assemblies have two inherent problems: thermal transfer from the inner layers and reliable, high-density interconnections among all substrates. This paper addresses the result of research on z-axis interconnects suitable for 3-D processor modules. We discuss the advantages and disadvantages for the intended system. One selected interconnection media, which is manufactured by Shin-Etsu, is based on metal wires embedded in a matrix of polymeric material. The wires protrude from the surface of the polymer film. By compressing this material between substrates, contact is made between metallized gold pads on the substrates via the embedded wires. The Shin-Etsu connector allows connections among multiple substrates at 0.5-mm pitch without the need for precision connector alignment because it contains redundant wires at very fine pitch. This paper describes the testing program to determine connector performance and reliability. Daisy chain test vehicles using gold metallization on ceramic substrates were fabricated, assembled and subjected to temperature cycling. Initial test results indicated an incompatibility between the connector material and the substrate, which led to hardware revisions. Daisy chains of 2500 z-axis interconnects have been subjected to over 800 temperature cycles from -45 °C to +85 °C. The resulting system appears to offer a reliable, high-density z-axis interconnection method.

3 citations


01 Jan 2001
TL;DR: In this article, the authors evaluated the effect of physical design on embedded resistors and found that resistors less than lOmil wide or one square in aspect ratio had much higher tolerance and variation than the others.
Abstract: This work was aimed at the RF performance of embedded resistors in LTCC, with tight tolerance, and low variation in resistance value, as basic required properties. In order to conduct this performance evaluation, two test vehicles were designed; one to evaluate the effect of physical design on embedded resistors, the other for characterization at high frequencies. DuPont 951 Green Tapes and CF021 resistor paste (100Ω/sq.) were employed to fabricate the substrates that were cofired at 875°C for 15 minutes. A four-probe Kelvin contact method and the HP-4263 LCR meter were used for the direct current (DC) resistance measurement, and an HP network analyzer was used for impedance measurements. It was found that although the majority of resistors had a 3a tolerance of 20∼30%, resistors less than lOmil wide or one square in aspect ratio had much higher tolerance and variation than the others. For the 2 to 5 square resistors in a certain width, the tolerance varied little. The apparent sheet resistivity demonstrated negative variation for resistors under 2 square and positive for over 2 square in aspect ratio. In a substrate with two resistor layers, the tolerance of most resistors on the upper layer was less than 15%, half of that on the lower layer, while their variation of apparent sheet resistivity were similar. Unlike the resistor width and aspect ratio, the overlap and extension had little influence on the tolerance and variation due to the short diffusion distance between termination and resistor. It is recommended that for low tolerance and low variation design, the preferred options are 20mil to 35mil width for one (1) to five (5) square aspect ratio, 10mil overlap and 5mil extension, and most importantly, no other embedded passives on the layers just over or under the resistors. With this design and the regular LTCC fabrication process, a tolerance less than 15% and variation no more than ± 5% have been achieved repeatedly in this work.

1 citations