Frederick A. Perner

Bio: Frederick A. Perner is an academic researcher from Hewlett-Packard. The author has contributed to research in topics: Memory cell & Sense amplifier. The author has an hindex of 35, co-authored 234 publications receiving 3729 citations. Previous affiliations of Frederick A. Perner include Samsung & Avago Technologies.

Magnetic memory device

Abstract: The present invention provides a magnetic memory device that includes a magnetic memory cell switchable between two states by the application of a magnetic field wherein the magnetic field for such switching is dependent in part on a memory cell temperature. The device further includes at least one heater element proximate to the magnetic memory cell and series connected with the magnetic memory cell for heating of the magnetic memory cell. The device also includes a circuit for selectively applying the electrical current through the at least one heater element so as to heat the cell and facilitate cell state-switching.

Write circuit for large MRAM arrays

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

System and method for sensing memory cells of an array of memory cells

Abstract: The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells. A method of the invention includes electrically connecting multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells; and sensing logic states of the multiple memory cells.

Magnetic random access memory (MRAM) device including differential sense amplifiers

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a differential amplifier, a first current mode preamplifier coupled to a sense node of the differential amplifier, and a second current mode preamplifier coupled to a reference node of the differential amplifier. During a read operation, the first preamplifier applies a regulated voltage to the selected memory cell, and the second preamplifier applies a regulated voltage to a reference cell. A sense current flows through the selected memory cell and to the sense node of the differential amplifier, while a reference current flows through the reference cell and to the reference node of the differential amplifier. Resulting is a differential voltage across sense and reference nodes. The differential voltage indicates whether a logic value of ‘0’ or ‘1’ is stored in the selected memory cell.

Lognormal switching times for titanium dioxide bipolar memristors: origin and resolution

Abstract: We measured the switching time statistics for a TiO2 memristor and found that they followed a lognormal distribution, which is a potentially serious problem for computer memory and data storage applications. We examined the underlying physical phenomena that determine the switching statistics and proposed a simple analytical model for the distribution based on the drift/diffusion equation and previously measured nonlinear drift behavior. We designed a closed-loop switching protocol that dramatically narrows the time distribution, which can significantly improve memory circuit performance and reliability.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine.

Abstract: Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small-scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High-precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single-layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible.

Resistance change memory device

Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm

Abstract: Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.

A review of emerging non-volatile memory (NVM) technologies and applications

Abstract: This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power ( e.g. , mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g. , neuromorphic computing, hardware security, etc . In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.