G. Bai

Bio: G. Bai is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Very-large-scale integration & Voltage drop. The author has an hindex of 5, co-authored 5 publications receiving 178 citations.

Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

Abstract: This paper presents techniques to include the effect of supply voltage noise on the circuit propagation delay of a digital VLSI circuit. The proposed methods rely on an input-independent approach to calculate the logic gate's worst-case power supply noise. A quasi-static timing analysis is then applied to derive a tight upper-bound on the delay for a selected path with power supply noise effects. This upper-bound can be further reduced by considering the logic constraints and dependencies in the circuit. Experimental results for ISCAS-85 benchmark circuits are presented using the techniques described in the paper. HSPICE simulation results are also used to validate our work.

Simulation and optimization of the power distribution network in VLSI circuits

Abstract: In this paper, we present simulation techniques to estimate the worst-case voltage variation using an RC model for the power distribution network. Pattern independent maximum envelope currents are used as a periodic input for performing the frequency-domain steady-state simulation of the linear RC circuit to evaluate the worst-case instantaneous voltage drop for the RC power distribution networks. The proposed technique unlike existing techniques, is guaranteed to give the maximum voltage drop at nodes in the RC power distribution network. We present experimental results to compare the frequency-domain and time-domain simulation techniques for estimating the maximum instantaneous voltage drop. We also present frequency domain sensitivity analysis based decoupling capacitance placement for reducing the voltage variation in the power distribution network. Experimental results on circuits extracted from layout are presented to validate the simulation and optimization techniques.

Simultaneous switching noise and resonance analysis of on-chip power distribution network

Abstract: This paper presents a frequency-domain technique for finding the worst-case time-domain voltage variations in the RLC power bus of digital VLSI circuits. Pattern independent maximum envelope currents are used for the logic gates and macroblocks. The voltage drop/surge at a power bus node is expressed in term of the currents using sensitivity analysis. The sensitivity information together with an optimization procedure are applied to find the upper-bounds on the voltage variations at the targeted bus nodes. The resonance problem due to the on-chip RLC power distribution network is analyzed base on the frequency-domain sensitivity analysis. Comparisons to SPICE simulation of circuits extracted from layouts are used to validate our approach.

Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms

Abstract: This paper presents a genetic algorithm (GA) based method for finding the maximum voltage drop in the power bus of digital VLSI circuits. The worst-case voltage drop at a specified node in the power bus is defined as the fitness value for different input-vector pairs. A gate-level simulator and a sparse linear solver are applied to compute the fitness value. A sharing technique is applied to find the global optima accurately and rapidly. Comparisons with input-independent simulations for circuits extracted from layouts are used to validate our approach.

RC power bus maximum voltage drop in digital VLSI circuits

Abstract: This paper presents an input-independent method for finding bounds on the voltage drop in RC power bus in combinational macro-block circuits. The voltage at power bus nodes is expressed in terms of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous high-to-low, and low-to-high switching in a subinterval of a clock cycle. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes. The effects of signal statistical variations on the results are automatically included in our method. Comparisons to exhaustive HSPICE simulation of circuits extracted from layout are used to validate our approach.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

Abstract: The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

VLSI Test Principles and Architectures: Design for Testability

Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Table of Contents Chapter 1 - Introduction Chapter 2 - Design for Testability Chapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-Test Chapter 6 - Test Compression Chapter 7 - Logic Diagnosis Chapter 8 - Memory Testing and Built-In Self-Test Chapter 9 - Memory Diagnosis and Built-In Self-Repair Chapter 10 - Boundary Scan and Core-Based Testing Chapter 11 - Analog and Mixed-Signal Testing Chapter 12 - Test Technology Trends in the Nanometer Age

Hierarchical analysis of power distribution networks

Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.

Hierarchical analysis of power distribution networks

Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.