G. Chen

Bio: G. Chen is an academic researcher from Facebook. The author has contributed to research in topics: Compiler & Optimizing compiler. The author has an hindex of 1, co-authored 1 publications receiving 28 citations.

Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems

Abstract: Addressing power and energy consumption related issues early in the system design flow ensures good design and minimizes iterations for faster turnaround time. In particular, optimizations at software level, e.g., those supported by compilers, are very important for minimizing energy consumption of embedded applications. Recent research demonstrates that voltage islands provide the flexibility to reduce power by selectively shutting down the different regions of the chip and/or running the select parts of the chip at different voltage/frequency levels. As against most of the prior work on voltage islands that mainly focused on the architecture design and IP placement related issues, this paper studies the necessary software compiler support for voltage islands. Specifically, we focus on an embedded multiprocessor architecture that supports both voltage islands and control domains within these islands, and determine how an optimizing compiler can automatically map an embedded application onto this architecture. Such an automated support is critical since it is unrealistic to expect an application programmer to reach a good mapping correlating multiple factors such as performance and energy at the same time. Our experiments with the proposed compiler support show that our approach is very effective in reducing energy consumption. The experiments also show that the energy savings we achieve are consistent across a wide range of values of our major simulation parameters.

A DCM-Only Buck Regulator With Hysteretic-Assisted Adaptive Minimum-On-Time Control for Low-Power Microcontrollers

Abstract: A 40-mA buck regulator operating in the inherently stable Discontinuous Conduction Mode (DCM) for the entire load range is presented. A pulse frequency modulation control scheme is implemented using a proposed hysteretic-assisted adaptive minimum-on-time controller to automatically adapt the regulator to a wide range of operating scenarios in terms of input, output, and passive component values while ensuring compensationless DCM operation with minimized inductor peak current. Thus, compact silicon area, low quiescent current, high efficiency, and robust performance across all possible scenarios can be achieved without any calibration. Moreover, power gating is employed in the analog circuits of the proposed controller to further improve efficiency at sub-mA loads. The regulator is integrated within a low-power microcontroller in 90-nm CMOS to power its digital core while allowing maximum flexibility in the powering options of the microcontroller and the choice of the passive components. It occupies 0.1 mm2 and achieves 92% peak efficiency, and 78.5% and 86% efficiency at 200-μA and 40-mA loads, respectively. It handles an input in the range of 1.8–4.2 V, an output in the range of 0.9–1.4 V, an inductor in the range of 4.7–10 μH, and an output capacitor in the range of 2.2–10 μF without any calibration or reoptimization.

Optimising energy consumption of design patterns

Abstract: Software design patterns are widely used in software engineering to enhance productivity and maintainability. However, recent empirical studies revealed the high energy overhead in these patterns. Our vision is to automatically detect and transform design patterns during compilation for better energy efficiency without impacting existing coding practices. In this paper, we propose compiler transformations for two design patterns, Observer and Decorator, and perform an initial evaluation of their energy efficiency.

A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS

Abstract: The dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is proposed. Unlike conventional single-frequency SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency ( $\sim $ 2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A low-power 5-output 2 MHz/120 MHz design in 45 nm with 1.8 V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 V to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10 µH off-chip inductor, 2 nF on-chip capacitor for each 15 mA output and 4.5 nF for the 50 mA output. The peak efficiency is 73%, dynamic voltage scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-regulation transients.

Energy Transparency for Deeply Embedded Programs

Abstract: Energy transparency is a concept that makes a program’s energy consumption visible, from hardware up to software, through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, as well as help both programmers and operating systems make energy-aware decisions. In this article, we focus on deeply embedded devices, typically used for Internet of Things (IoT) applications, and demonstrate how to enable energy transparency through existing static resource analysis (SRA) techniques and a new target-agnostic profiling technique, without hardware energy measurements. Our novel mapping technique enables software energy consumption estimations at a higher level than the Instruction Set Architecture (ISA), namely the LLVM intermediate representation (IR) level, and therefore introduces energy transparency directly to the LLVM optimizer. We apply our energy estimation techniques to a comprehensive set of benchmarks, including single- and multithreaded embedded programs from two commonly used concurrency patterns: task farms and pipelines. Using SRA, our LLVM IR results demonstrate a high accuracy with a deviation in the range of 1% from the ISA SRA. Our profiling technique captures the actual energy consumption at the LLVM IR level with an average error of 3%.

A 1 A, Dual-Inductor 4-Output Buck Converter With 20 MHz/100 MHz Dual-Frequency Switching and Integrated Output Filters in 65 nm CMOS

Abstract: The dual-frequency dual-inductor multiple-output (DF-DIMO) buck converter topology is presented. The topology employs a dual-phase 20 MHz current-mode-controlled input stage to reduce the inductance required per phase to only 200 nH, and a 4-output 100 MHz comparator-controlled fully integrated output stage to reduce the capacitance required per output to 10 nF. In order to enable each output to handle up to 250 mA load with less than 40 mV voltage ripple, a third-order bond-wire-based notch filter is employed at each output for voltage ripple suppression. Additionally, the proposed design employs dynamic output re-ordering to enhance cross-regulation performance, interleaved pulse-skipping to enhance light-load efficiency and dynamic performance, and high-gain error amplifier in the output feedback loop to enhance DC load regulation. Targeting multi-core DSPs, the proposed design is implemented in standard 65 nm CMOS technology with 1.8 V input, and outputs in the range of 0.6– 1.2 V with a total load of 1 A. It achieves a peak efficiency of 74%, less than 40 mV output voltage ripple, 0.5 V/70 ns dynamic voltage scaling (DVS), and settling time of less than 85 ns for 125 mA load steps; all with no observable cross-regulation transients.